Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

15.5.2. Trace Subsystem

The CoreSight* trace subsystem provides a network of IP that can be used to generate trace messages and to transport those messages to an external debugger for post trace analysis.

The diagram below shows the trace bus connectivity highlighted in blue, and the trace-related IP blocks (ETMs, STM, ATB funnels, NOC trace observers and probes, ATB replicator, trace port interface unit, embedded trace FIFOs, embedded trace router, ATB sync/async bridges, ATB upsizer/downsizer) also highlighted in blue.

Figure 320. Block Diagram of Trace Subsystem Network