Visible to Intel only — GUID: lll1674596205492
Ixiasoft
Visible to Intel only — GUID: lll1674596205492
Ixiasoft
7.6.3. PSS Clock Group
The PSS clock group includes the clocks required by the PSS NoC and the associated peripherals. The clock manager also contains the CSR bits to control the clock enables that are implemented within the associated peripherals.
The following figure shows the block diagram for the PSS NoC clock trees and associated peripherals.
The following table shows the registers used to program the clocks.
Clock Name | *.src | *.cnt (n+1 divider) | *.div (2^n divider) | Clock Gate (enable) |
---|---|---|---|---|
l3_main_free_clk | mainpllgrp.nocclk.src = 0 (Main_PLL_C3) = 1 (Peri_PLL_C1) |
--- | --- | --- |
l4_main_clk | --- | mainpllgrp.en.l4mainclken | ||
l4_mp_clk | mainpllgrp.nocdiv.l4mpclk | mainpllgrp.en.l4mpclken | ||
l4_sp_clk | mainpllgrp.nocdiv.l4spclk | mainpllgrp.en.l4spclken | ||
l4_sys_free_clk | mainpllgrp.nocdiv.l4sysfreeclk | --- | ||
SPIM: spim[1,0]_sclk_out | l4_main_clk | --- | --- | perpllgrp.en.spim_[1,0]_clken |
SPIS: spis[1,0]_sclk_in |
--- | --- | perpllgrp.en.spis_[1,0]_clken | |
DMA: dmac_core_clk, aclk_mi |
--- | --- | perpllgrp.en.dmaclken | |
DMA: hs_clk |
l4_mp_clk | --- | --- | perpllgrp.en.dmaclken |
USB2OTG: hclk, pmu_hclk, utmi_clk |
--- | --- | perpllgrp.en.usb2clken | |
I3C: core_clk |
--- | --- | perpllgrp.en.i3c_[1,0]_clken | |
I2C: pclk |
l4_sp_clk | --- | --- | perpllgrp.en.i2c_[1,0]_clken |
UART: pclk |
--- | --- | perpllgrp.en.uart_[1,0]_clken | |
SP TIMER: pclk |
--- | --- | perpllgrp.en.spitimer_[1,0]_clken |