Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public

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4.1.4. CCU System Integration

The following diagram shows the CCU system integration.

Figure 19. CCU System Integration

The following initiator ports interface to the CCU:

  • DSU: Cortex A55, Cortex A76 cores
  • F2H bridge: Agents in the FPGA fabric
  • TCU: To perform page table walks and to send/receive DVM v8.1 messages
  • PSS NoC: Enable HPS peripherals to access memory
  • GIC: To access LPI property and pending tables

The CCU interfaces to the following target ports:

  • MPFE: For accessing external SDRAM
  • MPFE registers: For accessing the MPFE registers
  • OCRAM: For accessing OCRAM
  • PSS NoC: Intended for fabric agents accessing HPS peripherals through F2H bridge
  • GIC: To access GIC registers

The clock manager provides clocks to the CCU.

The CCU issues a combined interrupt signal to GIC.

The reset manager controls the CCU reset, and also provides a Q-channel used to drain the F2H transactions before putting that interface in reset.