Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

4.3.4.4.1. MMU-600 TCU Hardware Configuration

These are the configuration parameters for the TCU.

Table 88.  TCU Configuration Parameters
Feature Parameter name Description Value
Walk cache depth TCUCFG_WCS1L0_DEPTH Number of walk cache entries in the TCU stage 1 level 0 cache. 256
TCUCFG_WCS1L1_DEPTH Number of walk cache entries in the TCU stage 1 level 1 cache. 256
TCUCFG_WCS1L2_DEPTH Number of walk cache entries in the TCU stage 1 level 2 cache. 256
TCUCFG_WCS1L3_DEPTH Number of walk cache entries in the TCU stage 1 level 3 cache. 256
TCUCFG_WCS2L0_DEPTH Number of walk cache entries in the TCU stage 2 level 0 cache. 256
TCUCFG_WCS2L1_DEPTH Number of walk cache entries in the TCU stage 2 level 1 cache. 256
TCUCFG_WCS2L2_DEPTH Number of walk cache entries in the TCU stage 2 level 2 cache. 256
TCUCFG_WCS2L3_DEPTH Number of walk cache entries in the TCU stage 2 level 3 cache. 256
Configuration cache depth TCUCFG_CC_DEPTH Number of entries in the TCU configuration cache. 256
Maximum number of DTI managers TCUCFG_NUM_TBU Maximum number of DTI managers, that is, DTI-TBU and DTI-ATS managers, that the TCU supports. 14

Maximum number of translation requests

TCUCFG_XLATE_SLOTS Maximum total number of translation requests from all DTI managers. 64

Number of parallel

PTWs

TCUCFG_PTW_SLOTS Number of translation requests that the TCU can manage in parallel. 32
Number of parallel configuration table walks TCUCFG_CTW_SLOTS Number of translations that can perform configuration table walks in parallel. 8
Number of DTI ATS managers TCUCFG_DTI_ATS Number of connected DTI-ATS managers. 0
DTI interface register slice TCUCFG_DTI_HNDSHK_MODE
You can configure a DTI interface register slice for improved timing. You can set this parameter to the following values:
  • 0 FULL: Fully registered, double-buffered register slice.
  • 1 FWD: Registered on forward path only, that is, the direction that TVALID on the DTI interface indicates.
  • 2 REV: Registered on reverse path only, that is, the direction that TREADY on the DTI interface indicates.
  • 3 BP: Bypass register slice.
3
Walk cache timing register slice TCUCFG_WC_LKPRSP_MODE

You can configure a register slice for improved walk cache timing:

  1. Registered.
  2. Not registered.
1
Configuration cache timing register slice TCUCFG_CC_LKPRSP_MODE

You can configure a register slice for improved configuration cache timing:

  1. Registered.
  2. Not registered.
1

QTW/DVM

interface data width

TCUCFG_QTW_DATA_WIDTH Queue and Table Walk (QTW) or Distributed Virtual Memory (DVM) interface data width. 64
Configuration cache index generation mode TCUCFG_CC_IDXGEN_MODE

You can select from two different configuration cache indexing schemes: 0 Polynomial. An indexing algorithm minimizes the likelihood of conflicts between cache entries. Arm recommends this setting for most systems.

1 Simple. Each StreamID and SubstreamID maps directly to a single configuration cache entry.

0