Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

13.4.4.5. Configuring the Quality of Service Logic

You can programmatically configure the QoS generator for each initiator through the QoS registers. There is a register set for each QoS generator.

Each QoS generator's register set includes the register types shown in the following table.

Table 390.  QoS Generator Register Types
Name Purpose
I_main_QosGenerator_Priority Specifies initiator urgencies. Register usage depends on the QoS generator mode.
I_main_QosGenerator_Mode Specifies the QoS generator mode (limiter, regulator, fixed, or bypass).
I_main_QosGenerator_Bandwidth Specifies the bandwidth threshold for limiter and regulator modes.
I_main_QosGenerator_Saturation Specifies the bandwidth measurement time window for limiter and regulator modes

The actual register names consist of the register type plus a prefix specific to the QoS generator. For example, the HPS CCU cache initiator 0 registers are:

  • ccu_dmi0_I_main_QosGenerator_Priority
  • ccu_dmi0_I_main_QosGenerator_Mode
  • ccu_dmi0_I_main_QosGenerator_Bandwidth
  • ccu_dmi0_I_main_QosGenerator_Saturation
  • ccu_dmi0_I_main_QosGenerator_ExtControl

The following table shows the QoS register name prefixes.

Table 391.  QoS Register Name Prefixes
Register Name Purpose
HPS CCU cache initiator 0 ccu_dmi0_
HPS CCU cache initiator 1 ccu_dmi1_
F2SDRAM Bridge tbu2noc_
CCU_IOS ccu_ios_
DMA_TBU dma_tbu_m_
EMAC_TBU emac_tbu_m_
IO_TBU io_tbu_m_
SDM_TBU sdm_tbu_m_

The following block diagram shows a graphical representation of the MPFE QoS Network-on-Chip.

Figure 310. MPFE QoS Network-on-Chip