Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.1.5.3.1. MDIO Interface

The MDIO interface signals are synchronous to l4_sp_clk in all supported modes.
Note: The MDIO interface signals can be routed to both the HPS I/O and FPGA I/O.
Table 114.  MDIO Interface for HPS and FPGA I/O
Signal HPS I/O Pin Name Direction Width Description
emac*_mdio_mac_mdi MDIO*_MDIO In 1 Management Data In.

The PHY generates this signal to transfer register data during a read operation. This signal is driven synchronously with the gmii_mdc_o clock.

emac*_mdio_mac_mdo Out 1 Management Data Out.

The EMAC uses this signal to transfer control and data information to the PHY

.
emac*_mdio_mac_mdoe Out 1 Management Data Output Enable.

This signal is asserted whenever valid data is driven on the gmii_mdo_o signal and can be used as a tri-state control for the gmii_mdo_o FPGA I/O tri-state output buffers. The active state of this signal is high.

emac*_mdio_mac_mdc MDIO*_MDC Out 1 Management Data Clock.

The EMAC provides timing reference for the gmii_mdi_i and gmii_mdo_o signals on GMII mode through this aperiodic clock. The maximum frequency of this clock is 2.5 MHz. This clock is generated from the application clock through a clock divider.

Note: * stands for the EMAC peripheral number.