Visible to Intel only — GUID: nqi1673393433118
Ixiasoft
Visible to Intel only — GUID: nqi1673393433118
Ixiasoft
5.1.5.3.1. MDIO Interface
Signal | HPS I/O Pin Name | Direction | Width | Description |
---|---|---|---|---|
emac*_mdio_mac_mdi | MDIO*_MDIO | In | 1 | Management Data In. The PHY generates this signal to transfer register data during a read operation. This signal is driven synchronously with the gmii_mdc_o clock. |
emac*_mdio_mac_mdo | Out | 1 | Management Data Out. The EMAC uses this signal to transfer control and data information to the PHY . |
|
emac*_mdio_mac_mdoe | Out | 1 | Management Data Output Enable. This signal is asserted whenever valid data is driven on the gmii_mdo_o signal and can be used as a tri-state control for the gmii_mdo_o FPGA I/O tri-state output buffers. The active state of this signal is high. |
|
emac*_mdio_mac_mdc | MDIO*_MDC | Out | 1 | Management Data Clock. The EMAC provides timing reference for the gmii_mdi_i and gmii_mdo_o signals on GMII mode through this aperiodic clock. The maximum frequency of this clock is 2.5 MHz. This clock is generated from the application clock through a clock divider. |