Visible to Intel only — GUID: wby1673376726733
Ixiasoft
Visible to Intel only — GUID: wby1673376726733
Ixiasoft
5.5.6.6.2. Input Enable Signal Generation
Each one of the data pins (DQ pin) and the DQS pin requires an input enable (OE) control signal that must be set in the appropriate time, so the signals received from the memory device can be correctly captured. The hardware that controls the generation of the input enable (IE) signal is similar to the one for the OE signal generation in the write path described earlier. In this case, the dfi_rddata_en_p0/p1 signals from the memory controller are used. The phy_ie_timing_reg register is used to control the mechanism to generate the IE signals. Initially, the dfi_rddata_en signal is delayed a configurable number of clk_phy clock cycles to line it up with the true (normal) DFI read data position. This implies that some functional blocks are required to operate with this delayed signal (this is the case of the TSEL signal generators). The number of cycles to be delayed is defined in the rddata_en_ie_dly field. The setting and clearing of the IE signal also can be delayed. For this, the IE signal for DQ pins is controlled with the dq_ie_start and dq_ie_stop fields. Similarly, the IE signal for the DQS pin is controlled with the dqs_ie_start and dqs_ie_stop fields. The setting and clearing times for IE signals can be adjusted with a ½ clk_phy clock cycle resolution.