Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.1.6.2.11.2. RX DMA Bus Error Handling Flow

If bus error is detected by the EMAC while fetching the RX descriptors from the system memory, it stops fetching descriptors and ignores descriptors yet to be fetched as a part of burst. However, it processes all the normal pre-fetched descriptors (if any) in the descriptor cache memory. While processing the descriptor where the bus error is detected, the packet transfer to the system memory is terminated forcibly by flushing the current packet in the RX queue. The EMAC completes any pending outstanding read/write requests on the RX channel. Also, EMAC attempts to close the descriptor with the error status (bit[15] =1 and bit[19:16] = 4’h1000 of RDES3) and then automatically stops the corresponding RX DMA channel.

If bus error is detected by the EMAC while transferring RX packet data to the system memory, EMAC stops fetching descriptors, stops packet data writes and also ignores descriptors yet to be fetched as a part of burst. The packet transfer to system memory is terminated forcibly by flushing the current packet in the RX queue. The EMAC completes any pending outstanding read/write requests on the RX channel. Also, it makes an attempt to close the descriptor with the error status (bit[15] =1 and bit[19:16] = 4’h1000 of RDES3) and then automatically stops the corresponding RX DMA channel.

If bus error is detected by the EMAC while writing back the descriptor to the system memory, EMAC stops fetching descriptors, stops packet data writes and ignores descriptors yet to be fetched as a part of burst. The packet transfer to system memory is terminated forcibly by flushing the current packet in the RX queue. The EMAC completes pending outstanding read/write requests on the RX channel and then it stops the corresponding RX DMA channel. In this case, the error status (bit[15] =1 and bit[19:16] = 4’h1000 of RDES3) write may not be successful as bus error is detected while writing back the descriptor itself.

When a RX DMA channel is stopped by the EMAC due to a bus error, the software driver is expected to follow the steps as described in Handling Bus Errors and Recovery. The software driver can optionally program the bit[31], RPF field of the DMA_CHx_Rx_Control register to prevent any head of the line (HOL) blocking of the other DMA channels which are not stopped. When this bit is 1 and corresponding DMA is stopped (either by software or EMAC) the RX packets routed to that RX channel are automatically flushed in the RX queues. Later, when the DMA is restarted by the software driver, the new packets received in the EMAC are routed to the RX DMA channel.
Note:
  • RPF = 1: Dynamic mapping causes flushing of packets from unintended queues to the stopped RX DMA
  • RPF = 0: When one of the RX DMA channels is stopped, it causes unintended stopping of RX DMA channels