Visible to Intel only — GUID: xme1676325057681
Ixiasoft
Visible to Intel only — GUID: xme1676325057681
Ixiasoft
11.1. Bridges Differences Among Intel SoC Device Families
The following table shows the differences of the HPS bridges between various device families.
HPS-FPGA Bridge Feature | Cyclone® V SoC, Arria® V SoC |
Arria® 10 SoC | Stratix® 10 SoC |
Intel® Agilex™ 7 F-Series/I-Series/ M-Series SoC |
Agilex™ 5 E-Series/D-Series SoC |
---|---|---|---|---|---|
H2F | 32-, 64-, or 128-bit | 32-, 64-, or 128-bit | 32-, 64-, or 128-bit | 32-, 64-, or 128-bit | 32-, 64-, or 128-bit |
LWH2F | 32-bit | 32-bit | 32-bit | 32-bit | 32-bit |
F2H | 32-, 64-, or 128-bit | 32-, 64-, or 128-bit | 128-bit | Single port: 128-, 256-, or 512-bit |
256-bit |
F2SDRAM | 32-, 64-, or 128-bit | 32-, 64-, or 128-bit | 32-, 64-, or 128-bit | 64-, 128-, or 256-bit | |
Protocol Support | AMBA 3 AXI3 | AMBA 3 AXI3 | AMBA 4 AXI4 + AMBA 4 ACE-Lite | AMBA 4 AXI4 + AMBA 4 ACE-Lite | AMBA 4 AXI4 + AMBA 4 ACE-Lite + AMBA 5 AXI5 |
Non-coherent traffic from fabric agents follows a 256-bits AXI F2SDRAM port based direct path to DRAM through the MPFE wrapper. Coherent traffic uses a 256-bits ACE-lite F2H port which leads the transaction into the cache coherent CCU interconnect within the application processor subsystem (APS) partition.