Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

15.5.1.4. Debug Reset

The Agilex™ 5 HPS initiates debug subsystem reset when either software writes to a register bit in the reset manager, or an external debugger requests a reset through JTAG via the Arm* DAP SWJ-DP. A debug reset only impacts the debug subsystem. The rest of the HPS remains operational.

For more details of the full debug reset state machine which controls the complete debug reset sequence including a hardware controlled fence and drain of all debug traffic prior to asserting the debug subsystem reset, refer to the CoreSight Debug and Trace Resets section.