Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

12.2.6.12. Preserving SDRAM contents

There are two types of reset – one which preserves the contents of the DDR memory, and one which does not. The contents can be preserved on HPS cold, watchdog, and warm resets. The following table shows the reset types and their corresponding behavior.

Table 364.  Preserving SDRAM Contents
EVENT EVENT trigger Pre-EVENT trigger setup Post-EVENT trigger execution SDRAM preserved?
HPS Warm Reset
  • SW/Mailbox
  • Watchdog
  • Reset_Mgr.hdsktimeout = 0x2800
  • Reset_Mgr.hdsken.etrstallen = 1’b1
  • Reset_Mgr.hdsken.fpgahsen = 1’b1
  • Reset_Mgr.hdsken.f2soc_flush = 1’b1
  • Reset_Mgr.hdsken.f2sdram_flush = 1’b1
  • Reset_Mgr.hdsken.soc2fpga_flush = 1’b1
  • Reset_Mgr.hdsken.lwsoc2fpga_flush = 1’b1
  • Reset_Mgr.hdsken.emif_flush = 1’b1
  • L1/L2/L3 cache flush is not performed.
  • Fence & Drain is performed.
  • HPS Warm or Cold Reset is performed, and HMC is not reset.
Yes
HPS Cold Reset
  • SW/Mailbox
  • HPS_COLD_nRESET pin
  • Watchdog

To preserve SDRAM contents, EMIF fence and drain must be enabled. If enabled (Reset_Mgr.hdsken.emif_flush = 1), the reset manager hardware issues a fence and drain request to the MPFE by asserting the Reset_Mgr.hdskreq.emif_flush_req signal. The MPFE then stops accepting new read or write requests. The MPFE keeps track of how many transactions there are in flight at any time, so once it has seen the fence and drain request and all the outstanding transactions have completed, the MPFE issues an acknowledge to the Reset Manager by asserting the Reset_Mgr.hdskack.emif_flush_ack signal to indicate that it is safe to actually perform the reset. At this point, the IOBank is not reset, and the SDRAM contents can be assumed to be preserved. If the reset manager does not receive an acknowledgment within a specified period (10,000 cycles), then it resets the MPFE regardless.

If EMIF fence and drain is not enabled (Reset_Mgr.hdsken.emif_flush = 0), then the IOBank is reset to ensure that any outstanding transactions are cleared. This also causes the IOBank to undergo training, and the SDRAM contents should be assumed to be lost.

See also the Fence and Drain registers and the Request and Acknowledge registers in the HPS Register Map located in Reset_Mgr.hdsken, Reset_Mgr.hdskreq, and Reset_Mgr.hdskack.

For more information, refer to Address Map and Register Definitions section.