Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.1.5.1. HPS EMAC I/O Signals

There are three EMACs available in the HPS. The following table lists the EMAC signals that can be routed from the EMACs to the HPS I/O pins. These signals provide access to the RGMII interface.

Table 112.  HPS EMAC I/O Interface
Signal Name Platform Designer Port Name Direction Width Description

EMAC*_TX_CLK

emac[2:0]_phy_txclk_o

Out

1

In RGMII mode, this signal acts as the transmit clock to PHY (125/25/2.5 MHz in 1G/100M/10Mbps).

All PHY transmit signals generated by the EMAC are synchronous to this clock.

EMAC*_TXD[3:0]

PHY Transmit Data, routed from one of three groups of Platform Designer port signals.

emac[2:0]_phy_txd_o[3:0]

Out

4

This is a group of transmit data signals driven by the MAC. They have multiple functions depending on the selected PHY interface as described in the following list:

  • RGMII: Bits[3:0] provide the RGMII transmit data.
    • In RGMII 1000 Mbps mode, the data bus carries transmit data at double data rate and are sampled on both the rising and falling edges of the EMAC*_TX_CLK.
    • In RGMII 10/100 Mbps modes, the data bus is single data rate, synchronous to the rising edge of the EMAC*_TX_CLK.

The validity of the data is qualified with EMAC*_TX_CTL.

EMAC*_TX_CTL

PHY Transmit Data Enable, routed from one of three Platform Designer port signal

emac[2:0]_phy_txen

Out

1

This signal is driven by the EMAC component.

  • RGMII: This signal acts as the control signal for the transmit data, and is driven on both edges of the transmit clock, EMAC*_TX_CLK.

EMAC*_RX_CLK

Receive Clock, routed to one of three Platform Designer port signals.

emac[2:0]_clk_rx_i

In

1

In RGMII mode, this clock frequency is 125/25/2.5 MHz in 1G/100 M/10Mbps modes. It is provided by the external PHY. All PHY signals received by the EMAC are synchronous to this clock.

EMAC*_RXD[3:0]

PHY Receive Data, routed to one of three groups of Platform Designer port signals

emac[2:0]_phy_rxd[3:0]

In

4

This is a group of data signals received from the PHY. It has multiple functions depending on the selected PHY interface as described in the following list:

  • RGMII: Bits [3:0] provide the RGMII receive data.
    • In RGMII 1000 Mbps mode, data is received at double data rate with bits[3:0] valid on the rising and falling edges of EMAC*_RX_CLK.
    • In RGMII 10/100Mbps modes, data is received at single data rate with bits[3:0] valid on the rising edge of EMAC*_RX_CLK.

EMAC*_RX_CTL

PHY Receive Data Valid, routed to one of three groups of Platform Designer port signals

emac[2:0]_phy_rxdv

In

1

This signal is driven by the PHY and functions as the receive control signal used to qualify the data received on EMAC*_RXD[3:0].

  • RGMII: This signal is sampled both edges of the clock.

Synchronous to: clk_rx_312pt5_i, clk_rx_312pt5_180_i

Note: * is for the EMAC peripheral number.
Each EMAC module in the HPS supports one PHY interface. If you are using the HPS pins for interfacing to a PHY, the following diagrams show the interface options available depending on what PHY you choose.
Figure 52. HPS EMAC to RGMII PHY Interface