Visible to Intel only — GUID: tsn1673393431620
Ixiasoft
Visible to Intel only — GUID: tsn1673393431620
Ixiasoft
5.1.5.1. HPS EMAC I/O Signals
There are three EMACs available in the HPS. The following table lists the EMAC signals that can be routed from the EMACs to the HPS I/O pins. These signals provide access to the RGMII interface.
Signal Name | Platform Designer Port Name | Direction | Width | Description |
---|---|---|---|---|
EMAC*_TX_CLK |
emac[2:0]_phy_txclk_o |
Out |
1 |
In RGMII mode, this signal acts as the transmit clock to PHY (125/25/2.5 MHz in 1G/100M/10Mbps). All PHY transmit signals generated by the EMAC are synchronous to this clock. |
EMAC*_TXD[3:0] |
PHY Transmit Data, routed from one of three groups of Platform Designer port signals. emac[2:0]_phy_txd_o[3:0] |
Out |
4 |
This is a group of transmit data signals driven by the MAC. They have multiple functions depending on the selected PHY interface as described in the following list:
The validity of the data is qualified with EMAC*_TX_CTL. |
EMAC*_TX_CTL |
PHY Transmit Data Enable, routed from one of three Platform Designer port signal emac[2:0]_phy_txen |
Out |
1 |
This signal is driven by the EMAC component.
|
EMAC*_RX_CLK |
Receive Clock, routed to one of three Platform Designer port signals. emac[2:0]_clk_rx_i |
In |
1 |
In RGMII mode, this clock frequency is 125/25/2.5 MHz in 1G/100 M/10Mbps modes. It is provided by the external PHY. All PHY signals received by the EMAC are synchronous to this clock. |
EMAC*_RXD[3:0] |
PHY Receive Data, routed to one of three groups of Platform Designer port signals emac[2:0]_phy_rxd[3:0] |
In |
4 |
This is a group of data signals received from the PHY. It has multiple functions depending on the selected PHY interface as described in the following list:
|
EMAC*_RX_CTL |
PHY Receive Data Valid, routed to one of three groups of Platform Designer port signals emac[2:0]_phy_rxdv |
In |
1 |
This signal is driven by the PHY and functions as the receive control signal used to qualify the data received on EMAC*_RXD[3:0].
Synchronous to: clk_rx_312pt5_i, clk_rx_312pt5_180_i |