Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.10.5.2. FPGA Routing

Two sets of SPI Master and two sets of SPI Slave Pins are available for routing to the FPGA. The signal names are shown below.

Table 271.  SPI Master Signals for FPGA Routing

Signal Name

Signal Width

Direction

Description

spim_mosi_o

1

Out

Transmit data line for the SPI master

spim_miso_i

1

In

Receive data line for the SPI master

spim_ss_in_n

1

In

Master Contention Input

spim_mosi_oe

1

Out

Output enable for the SPI master

spim_ss0_n_o

1

Out

Slave Select 0

Slave select signal from SPI master

spim_ss1_n_o

1

Out

Slave Select 1

Allows second slave to be connected to this master

spim_ss2_n_o

1

Out

Slave Select 2

Allows third slave to be connected to this master

spim_ss3_n_o

1

Out

Slave Select 3

Allows fourth slave to be connected to this master

spim_sclk_out

1

Out

Serial clock output

Table 272.   SPI Slave Signals for FPGA Routing

Signal Name

Signal Width

Direction

Description

spis_miso_o

1

Out

Transmit data line for the SPI Slave

spis_mosi_i

1

In

Receive data line for the SPI Slave

spis_ss_in_n

1

Out

Master Contention Input

spis_miso_oe

1

Out

Output enable for the SPI Slave

spis_sclk_in

1

In

Serial clock input