Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.3.6.4.3.1. Operation in PIO Work Mode

The following commands are supported in the PIO work mode:

Page Read and Page Write: These commands allow reading or programming a data block that is composed from a specified number of NAND Flash memory pages. Both commands are translated into a series of low-level page read/page write, multi-plane page read/multi-plane page write, or cache read/cache program operations, depending on core configuration. Refer to Extended Functionality in Command Engine to see how valid transfer mode is selected.

  • Copyback: This command allows reading and writing back a data block that is composed of a specified number of NAND Flash memory pages. This command is translated into a series of low-level Copyback commands. Both the source and destination addresses need to point on the same BANK, LUN, and Plane. The host's software needs to follow NAND device addressing restrictions when it selects source and destination Flash pointers. Refer to Extended Functionality in Command Engine to see how valid transfer mode is selected.
  • Erase: This command allows erasing the content of the specified number of consecutive NAND Flash memory data blocks. This command is translated into a series of low-level block erase commands.
  • Reset: This command sends the Reset Command to the selected BANK/LUN. This command is translated into a low-level reset command. Different type of resets is supported (asynchronous reset, synchronous reset and LUN reset).
  • Set Features: This command is translated into the Set Feature command on the NAND Flash interface. This command needs to be used to switch ONFI device work mode. The Controller selects the same configuration for each LUN on selected bank, so LUN set feature commands will never be used.

In the PIO operation mode, the command registers to be used depend on the command to execute. The Command 0 register is used for all supported commands since writing to this register triggers the operation execution, because of this, the command register should be the last register to configure.

The following tables describe the structure of the Command registers that applies for each one of the commands supported. In the tables, if the description of a field does not indicate to which commands apply, this means that this field description applies for all the supported commands.

Command 0 (offset 0x0000) Description

Table 192.   Structure of Command 0 Register in PIO Mode
Bits Name Description
31:30 CT The 2'b01 value indicates the PIO work mode
29:27 Reserved Reserved
26:24 TRD_NUM

This field selects destination thread number for command. The software can select any available thread. Commands can be issued in parallel to all threads.

23:22 Reserved Reserved
21 DMA_SEL

Page Read / Page Program commands

This bit selects DMA engine. Options are:

0: DMA slave

1: DMA master

Reserved

Copyback / Block Erase / Reset / Set Features commands

Reserved

20 INT If this bit is set, then an interrupt should be issued after this operation is finished. The status of the triggered interrupt is reported in trdX_comp field in the trd_comp_intr_status (0x0138) register, where interrupt bit is selected by the thread number selected by the TRD_NUM field (one bit per thread).
19:16 VOL_ID This field must be set to 0.

15:0

CMD_TYPE

This field identifies the kind of operation that is executed by the controller.

Page Read command

This field encoding is as follows: 0x22PP, where "PP" is a number of sequential pages to transfer decoded as "PP+1" (0 means that one page is transferred).

Page Program command

This field encoding is as follows: 0x21PP, where "PP" is a number of sequential pages to transfer decoded as "PP+1" (zero means that one page is transferred).

CopyBack command

This field encoding is as follows: 0x12PP. Where "PP" is a number of sequential pages to transfer decoded as "PP+1" (zero means that one page is transferred)

Erase Block command

This field encoding is as follows:

0x10PP, where "PP" is a number of sequential blocks to erase decoded as

"PP+1" (zero means that one block is erased).

Reset command

This field encoding is as follows: 0x11PP. The PP parameter is used to select reset type:

0x00: asynchronous reset

0x01: synchronous reset

0x02: LUN reset

Set Feature command

This field encoding is as follows: 0x0100.

Command 1 (offset 0x0004) Description

Table 193.  Structure of Command 1 Register in PIO Mode
Bits Name Description
31:0 ROW_ADDRESS

Page Read/Page Program

This field contains operation Row Address.

Copy Back

This field contains operation Row Address for source location.

Erase Block command

This field contains operation Row Address of the first block to erase.

Reset command

This field contains the operation Row Address of the LUN to reset. This field is only valid for LUN reset.

Table 194.   Structure of Command 1 Register in PIO Mode for Set Features Command
Bit Name Description
31:8 Reserved

Set Features command

Reserved

7:0 FEATURE_ADDR

Set Features command

This field selects feature address. The address value is translated into the address that is sent with SET FEATURE command on the NAND Flash interface. Allowed values can be found in the NAND Flash device data sheet

Command 2 (offset 0x0008) Description

Table 195.   Structure of Command 2 Register in PIO Mode
Bit Name Description
31:0 MEM_ADDR_PTR_L

Page Read / Page Program commands

Host memory address required for DMA transfers. It is the lower address part.

Copy Back command

This field contains operation Row Address for target location.

RESERVED

Erase Block / Reset commands

Reserved – Not used

FEATURE_VAL

Set Features command

This field stores the feature data value. The FEATURE_VAL is sent with SET FEATURE command on the NAND Flash interface. Allowed values can be found in the NAND Flash device data sheet.

Command 3 (offset 0x000c) Description

Table 196.   Structure of Command 3 Register in PIO Mode
Bit Name Description
31:0 MEM_ADDR_PTR_H

Page Read / Page Program commands

Host memory address required for DMA transfers. It is the higher address part.

RESERVED

Copy Back / Erase Block / Reset / Set Features commands

Reserved – Not used

Command 4 (offset 0x0020) Description

Table 197.   Structure of Command 4 Register in PIO Mode
Bit Name Description
31:24 Bank

Page Read/Page Program/Copyback/Erase block commands

This field contains operation bank number. Only banks with physical devices connected should be selected (NAND device chip select). Only one chip is supported by HPS.

RESERVED

Reset/Set Features commands

Reserved – Not used

Command 5 (offset 0x0024) Description

Table 198.   Structure of Command 5 Register in PIO Mode
Bit Name Description
31:0 CTRL_ADDR_PTR_L

Page Read/Page Program

Host memory address required for Control Data DMA transfers. It is the lower address part.

RESERVED

Copyback/Erase block/Reset/Set Features commands

Reserved – Not used

Command 6 (offset 0x0028) Description

Table 199.  Structure of Command 6 Register in PIO Mode
Bit Name Description
31:0 CTRL_ADDR_PTR_H

Page Read/Page Program command

Host memory address required for Control Data DMA transfers. It is the higher address part.

RESERVED

Copyback/Erase block/Reset/Set Features commands

Reserved – Not used