Visible to Intel only — GUID: znq1673393447183
Ixiasoft
Visible to Intel only — GUID: znq1673393447183
Ixiasoft
5.1.6.2.8. DMA Start/Stop Operation
In addition to software based control, EMAC also supports sideband signals to control per-channel DMA start and stop. The final state of DMA start/stop depends on both sideband signals as well as software.
The software control to start/stop the Tx/Rx DMA, is by programing bit[0] (ST/SR field) of DMA_CH(#i)_Tx_Control or DMA_CH(#i)_Rx_Control register respectively. The per-channel sideband signals are combined with programmable start and stop control bits of the corresponding DMA channel to control the start/stop of the DMA.
When the DMA receives stop command by programming bit[0] (ST/SR field) of DMA_CH(#i)_Tx_Control/ DMA_CH(#i)_Rx_Control register, the DMA is stopped after completing the current packet transfer (if any). However, there can be descriptors in the memory cache which are already pre-fetched. The packets corresponding to such descriptors are not transferred. When the DMA is started again by the software by setting the bit[0] (ST/SR field) of the DMA_CH(#i)_Tx_Control or the DMA_CH(#i)_Rx_Control register, the DMA continues processing the descriptor where it was stopped.
Hardware ST/SR | Software ST/SR | Existing ST/SR | New ST/SR | Comment |
---|---|---|---|---|
0 | 0 | 0 | 0 | Default/Reset value |
0 to 1 | 0 | 0 | 1 | Hardware starts DMA |
0 | 0 to 1 | 0 | 1 | Software starts DMA |
1 | 1 | X | 1 | Hardware or software starts DMA |
1 to 0 | 1, 0 | 1 | 0 | Hardware stops DMA |
1, 0 | 1 to 0 | 1 | 0 | Software stops DMA |