Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.3.7.3. Device Layout Configuration

During the device discovery mechanism, the NAND controller is able to configure some of the NAND controller registers with the NAND device information. However, for raw NAND devices where there is no universally adopted protocol of defining the identification sequence, it is possible that the device is not identified correctly and the values in these registers may be incorrect. It is responsibility of the software running in the host to ensure that the correct values get programmed in the following registers:

  • nf_dev_layout (0x0424): setup correct value of pages per block and LUNs numbers.
  • Set or clear the device_16bit bit in the common_settings (0x1008) register to select correct value of device width.