Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.1.4.2. EMAC System Integration

The following figure shows the system integration of the EMAC with other blocks in the HPS.
Figure 51. EMAC System Integration

Each EMAC contains a dedicated DMA controller that manages Ethernet packets to and from the System Interconnect. The EMAC uses a descriptor ring protocol, where the descriptor contains an address to a buffer to fetch or store the packet data.

Each EMAC has an MDIO management port to send commands to the external PHY. This port can be implemented using the I2C modules in the HPS or the EMAC's MDIO interface.

All three EMACs have individual time reference based on internal Time of Day (ToD) counter. The HPS uses a 64-bit system timer for time reference. The FPGA fabric may implement a local ToD counter as a separate time reference for time. A precise relationship between HPS system timer and EMAC’s ToD, FPGA local ToD must be established in this case. The SMTG hub is implemented to capture concurrent triggers from multiple sources and maintain time synchronization between the HPS, one or more EMACs in the HPS or the FPGA fabric.

Each EMAC has an IEEE 1588 Timestamp interface with 2.5 ns resolution. The reference clock for the time stamp can be provided by the Clock Manager (tsn_ptp_clk) or the FPGA fabric (f2h_ptp_ref_clk). The clock reference is selected by the ptp_clk_sel bit in the tsn_global register in the system manager.

The EMAC can interface with external PHY directly using the RGMII interface for the 10/100/1G Ethernet network through HPS pins or using the GMII interface through the FPGA fabric to support up to 2.5 Gbps transmission medium.
Note:
  1. The HPS is only able to support a maximum of 2 EMAC instances using the HPS RGMII interface due to the HPS IO pin number restrictions.
  2. The EMAC GMII interfaces must be exposed to the FPGA fabric for RGMII, SGMII and SGMII+ implementation which requires additional soft IP adapter logic.