Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

4.3.5.2. MMU-600 TBU Configuration Signals

The values of the configuration straps for the TBU instances are shown in the following table.

Table 94.  TBU Configuration Signals

Signal

Description

IO TBU

TSN

TBU

FPGA TBU

FPGA

COH

TBU

ns_sid_high[23:TBUCFG_SID_WI DTH]

Provides the high-order StreamID bits for all transactions with a non-secure StreamID that pass through the TBU.

0

0

0

0

s_sid_high[23:TBUCFG_SID_WID TH]

Provides the high-order StreamID bits for all transactions with asecure StreamID that pass through the TBU.

0

0

0

0

max_tok_trans[log2(TBUCFG_XLA TE_SLOTS)-1:0]

Indicates the number of DTI translation tokens to request when connecting to the TCU, minus 1.

255

255

255

255

pcie_mode

You must tie this signal HIGH when the TBU is connected to a PCIe interface.

0

0

0

0

sec_override

When HIGH, certain registers are accessible to non-secure accesses from reset, as the TBU_SCR register settings describe.

0

0

0

0

ecorevnum[3:0]

Tie this signal to 0 unless directed otherwise by Arm.

0

0

0

0

utlb_roundrobin

Defines the Micro TLB entry replacement policy. When LOW, the Micro TLB uses a Pseudo Least Recently Used (PLRU) replacement policy. When HIGH, the Micro TLB uses a round-robin replacement policy.

0

0

0

0

cmo_disable

To disable cache maintenance operations, tie this signal HIGH.

When this signal is HIGH, the following transactions are always aborted with an SLVERR response:

  • CleanInvalid
  • CleanShared
  • CleanSharedPersist
  • MakeInvalid

0

0

0

0