Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.7.5.6. Local Memory Buffer

The USB OTG controller has three local SRAM memory buffers.
  • The write FIFO buffer is a 128 × 32-bit memory (512 total bytes)
  • The read FIFO buffer is a 32 × 32-bit memory (128 total bytes)
  • The ECC buffer is a 96 × 16-bit memory (192 total bytes)

The SPRAM is a 8192 x 35-bit (32 data bits and 3 control bits) memory and includes support for ECC (Error Checking and Correction). The ECC block is integrated around a memory wrapper. It provides outputs to notify the system manager when single-bit correctable errors are detected (and corrected) and when double-bit uncorrectable errors are detected. The ECC logic also allows the injection of single- and double-bit errors for test purposes. The ECC feature is disabled by default. It must be initialized to enable the ECC function.