Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.6.5.10.6. Maximum USB Bandwidth

To match the USB spec-defined maximum bandwidth, the system bus bandwidth must be greater than the USB device or host maximum bandwidth. The system bus bandwidth requirement of the USB device is provided in the following table.

Table 238.  Required System Bus Bandwidth for USB Device
USB Device System Bus Bandwidth
USB 3.1 2.43 Gbps

The system bus bandwidth is requirement of the USB Hosts is provided in the following table:

Table 239.  Required System Bus Bandwidth for USB Host
USB Host System Bus Bandwidth
USB 3.1

(2.43*Number of bus instance + 0.5 * Number of High-speed bus instances) Gbps = (2.43*1 + 0.5*1) Gbps =2.93Gbps

The raw bandwidth of the system bus is (bus clock frequency * master-bus-data-width/8) Bytes/Second. For the Agilex™ 5, system bus frequency is 400 MHz and databus width is 64-bit. So, the raw system bus bandwidth is:

(400MHz*64/8) Bytes/s = 3.2 GBps

The PIPE clock frequency for USB 3.1 is fixed to 250 MHz with data width as 16-bit.

The raw bandwidth at PIPE interface is:

(250 MHz*16/8) Bytes/s = 500 MBps

To achieve higher performance, system bus should be used for large transfers. As transfer sizes become smaller, the throughput of a bus can fall rapidly.