Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public

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11.6. Bridges Clocks and Resets

This section describes the clocks and resets for the bridges.

Table 344.  Bridges Clocks and Resets
Bridge Reset Clock
H2F hps2fpga_axi_reset hps2fpga_axi_clock
LWH2F lwhps2fpga_axi_reset lwhps2fpga_axi_clock
F2H fpga2hps_reset fpga2hps_clock
F2SDRAM f2sdram_axi_reset f2sdram_axi_clock