Visible to Intel only — GUID: dmm1677549723967
Ixiasoft
Visible to Intel only — GUID: dmm1677549723967
Ixiasoft
A.2.6.10. Interrupts
All interrupt sources are combined to create a single level-sensitive, active-high interrupt (qspi_intr). Software can determine the source of the interrupt by reading the interrupt status register (irqstat). By default, the interrupt source is cleared when software writes a one (1) to the interrupt status register. The interrupts are individually maskable through the interrupt mask register (irqmask). Interrupt Sources in the irqstat Register lists the interrupt sources in the irqstat register.
Interrupt Source | Description |
---|---|
Underflow detected | When 0, no underflow has been detected. When 1, the data target write data is being supplied too slowly. This situation can occur when data target write data is being supplied too slowly to keep up with the requested write operation. This bit is reset only by a system reset and cleared only when a 1 is written to it. |
Indirect operation complete | The controller has completed a triggered indirect operation. |
Indirect read reject | An indirect operation was requested but could not be accepted because two indirect operations are already in the queue. |
Protected area write attempt | A write to a protected area was attempted and rejected. |
Illegal data target access detected | An illegal data target access has been detected. Data target wrapping bursts and the use of split and retry accesses can cause this interrupt. It is usually an indicator that soft masters in the FPGA fabric are attempting to access the HPS in an unsupported way. |
Transfer watermark reached | The indirect transfer watermark level has been reached. |
Indirect read partition overflow | Indirect read partition of SRAM is full and unable to immediately complete indirect operation |