Visible to Intel only — GUID: qky1675713026823
Ixiasoft
Visible to Intel only — GUID: qky1675713026823
Ixiasoft
8.2. Reset Manager Use Cases
The reset manager use cases are described below.
- Power-on-reset (POR): Reset everything. No flush and drain.
- HPS cold reset: Reset everything except logic in POR domain (like scratchpad registers). Flush and drain all HPS ports under reset manager control.
- HPS watchdog reset: Warm reset everything except debug/trace logic. Support debug through watchdog reset. Flush and drain all HPS ports under reset manager control. Watchdog reset is identical to warm reset, except the source of the reset request is different (that is, the request comes from the watchdog timer(s) instead of SDM).
- HPS warm reset: Warm reset everything except debug/trace logic. Support debug through warm reset. Flush and drain all HPS ports under reset manager control. Warm reset is identical to watchdog reset, except that the source of the reset request is different (that is, the request comes from SDM).
- Debug and trace reset: Either software or the debugger resets debug and trace logic while the rest of the HPS remains functional. All traffic into and out of the CoreSight system is fenced and drained under reset manager control.
- Bridge reset: Reset F2H and H2F bridges to clear hung bridges while HPS remains functional. Flush and drain of all bridge traffic is under reset manager control.
- Core0, Core1, Core2, and Core3 warm reset: Core writes to its RMR_EL3[RR] register then executes WFI. The DSU warm resets the requesting core without reset manager intervention.
The following table provides an overview of the reasons why the various reset types are utilized on the HPS. Some portions of the HPS might need to be idled before reset is asserted to make sure any in-process transactions are completed.
Reset | Requestor | Why? | Idle before assertion? | ||||
---|---|---|---|---|---|---|---|
PSI Link |
Debug |
SDRAM | Bridges | CPUs | |||
HPS POR | POR, voltage range/tamper issue |
|
Not | Not | Not | Not | Not |
PS POR | HPS_VCCL voltage range/tamper issue |
Voltage tamper/out of range event on VCCL_HPS voltages. | Not | Not | Not | Not | Not |
HPS Cold | HPS Cold Reset Pin or Mailbox message or Watchdog |
The HPS needs to be reset without affecting the state of POR- only registers in the PSI link, clock manager, reset manager, secure manager, system manager, or JTAG TAP. Also signals a cold reset to the fabric. Use cases include:
|
Yes | Yes | Yes | Yes | Not |
Watchdog Timeout | Watchdog timers | The HPS is not operating as expected, because software has either locked up or has run away. A reset is needed to bring the HPS back to an operating state. This is managed by the SDM so it can clean up any transactions (Flash, DRAM accesses) prior to the reset. | Yes | Yes | Yes | Yes | Not |
HPS Warm | Mailbox or Watchdog | The HPS needs to be reset without affecting the state of POR or cold registers in the PSI link, clock manager, reset manager, secure manager, system manager, or JTAG TAP. Also signals a warm reset to the fabric. Use cases include:
|
Yes | Yes | Yes | Yes | Not |
Debug Reset | Debugger SW | The debugger has lost communication with the device. The user wants to bring the debug and trace logic back to its cold reset state to re-establish communication. | Not | Yes | Not | Not | Not |
Peripheral & Bridge SW Reset | ARM SW | Software wants to bring one or more peripherals back to its cold reset state. Bridges put in reset before an FPGA reconfiguration are performed. | Not | Not | Not | Not | Not |
CPU SW Warm Reset | ARM SW | The CPU wants to change its operating state, therefore, the request to be reset by writing to the RMR_EL3[RR] bit and executing a WFI instruction. DSU resets the requesting core without reset manager intervention. The core reset status is not tracked in the reset manager | Not | Not | Not | Not | Selected CPU must be in WFI |