Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

12.3.1.5.2. Configure External PHY RGMII-Internal Delay (RGMII-ID)

In RGMII 2.0 specification, it introduced the delay on-chip at the source. Devices which support the internal delay features are commonly referred as RGMII-ID. Agilex 5 HPS EMAC and HPS GMII-to-RGMII Adapter Intel FPGA IP do not support RGMII-ID but today most of the PHY do support RGMII 2.0.

The RGMII-ID provide you with a convenient way to configure PHY specific RX/TX clock delay register which can be used to adjust the timing of the clock signals to account for signal skew.

When selecting a PHY device, consider the desired Ethernet rate, available I/O and available transceivers, PHY devices that offer the RGMII-ID skew control feature, and device driver availability.