Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

15.5.2.2. System Trace Macrocell (STM)

A STM provides an AXI memory-mapped interface that supports instrumentation trace from multiple processors. STM also provides a HWEVENT interface for tracing signals within the system. For HWEVENT connectivity, refer to ATB IDs. You can enable timestamps to provide coarse grain timestamping of STM trace messages. The generated messages are transported out of the STM on a 64-bit ATB interface. Since the trace infrastructure is 32-bit wide, an ATB downsizer decreases the ATB size from 64 to 32-bits before connecting to the main ATB funnel.