Visible to Intel only — GUID: aui1678722653815
Ixiasoft
Visible to Intel only — GUID: aui1678722653815
Ixiasoft
12.2.6.11. Clocks Circuitry
The IOBank provides a clock output for each of its initiator NIU ports that is to be used to clock the associated target NIU in either the MPFE or MPFE-lite, so that the two associated NIUs run asynchronously with each other. The Port 0 clock (32-bit controller) from IOBank_0 is also used as the MPFE_clk, and the Port 0 clock from the IOBank_1 is used as the MPFE_lite_clk. The MPFE_clk and MPFE_lite_clk are to be treated as being asynchronous to the other NIU clocks.
Additional details on MPFE clocks are available in the Clock Manager chapter.
The following diagram shows the clock connectivity for the MPFE and MPFE-lite.
Clock | Description |
---|---|
mpfe_clk |
Clock provided by IOBank0 for MPFE NoC, TBU, and the MPFE facing portion of the FPGA-to-SDRAM Bridge. Derived from IOBank Port 0 clock. |
mpfe_p1_clk |
Clock provided by IOBank0 for the IOBank0_P1 target NIU |
mpfe_csr_clk |
Clock provided by IOBank0 CSR port for the IOBank0_CSR and MPFE_lite_CSR target NIUs in MPFE as well as the MPFE_lite_csr initiator NIU in the MPFE-lite. |
IOBank1_p0_clk |
Clock provided by the IOBank1 for the IOBank1_P0 target NIU. This clock is not present on devices supporting a single IOBank. |
IOBank1_p1_clk |
Clock provided by the IOBank1 for the IOBank1_P1 target NIU. This clock is not present on devices supporting a single IOBank. |
IOBank1_csr_clk |
Clock provided by the IOBank1 for the IOBank1_CSR target NIU. This clock is not present on devices supporting a single IOBank. |
f2sdram_axi_clock |
Clock for the fabric facing portion of the FPGA-to-SDRAM. |
fpga2hps_clock |
Clock for the fabric facing portion of the FPGA-to-HPS. |