Visible to Intel only — GUID: uev1678722647948
Ixiasoft
Visible to Intel only — GUID: uev1678722647948
Ixiasoft
12.2.6.7. MPFE NoC
The MPFE NOC is the main interconnect to route read/write traffic from the Fabric or the HPS to one or two IOBank blocks, depending on the operating mode.
The MPFE NOC has seven initiator ports and seven target ports. Three of the initiator ports (F2SDRAM 256/128/64-bit) and one of the target ports (NoC-to-TBU) form a width adaption network between the Fabric and the MPFE_TBU. The four remaining initiator ports receive post-TBU transactions (TBU-to-NoC), memory accesses from the CCU (CCU_DMI0 and CCU_DMI1) and HPS accesses to the MPFE/IOBank CSRs (MPFE_CSR). The six remaining target ports send transactions to the IOBank0 CSR (IOBank0_CSR), Port 0 (IOBank0_P0), and Port 1 (IOBank0_P1) interfaces, as well as the MPFE-lite CSR (MPFE_lite_CSR), Port 0 (MPFE_lite_P0), and Port 1 (MPFE_lite_P1) interfaces for forwarding to the IOBank1.
Initiators | ||||||
---|---|---|---|---|---|---|
F2SDRAM | CCU_DMI0 | CCU_DMI1 | MPFE_CSR | TBU2NOC | ||
Targets | IOBank0_P0 | √ | √ | |||
IOBank0_P1 | √ | √ | √ | |||
IOBank0_CSR | √ | |||||
MPFE_lite_P0 | √ | √ | ||||
MPFE_lite_P1 | √ | √ | ||||
MPFE_lite_CSR | √ | |||||
NoC-to-TBU | √ |