Visible to Intel only — GUID: ezv1673379983683
Ixiasoft
Visible to Intel only — GUID: ezv1673379983683
Ixiasoft
5.13.4. UART Controller System Integration
Block |
Description |
---|---|
Slave interface |
Slave interface between the component and L4 peripheral bus |
Register block |
Provides main UART control, status, and interrupt generation functions. |
FIFO buffer |
Provides FIFO buffer control and storage. |
Baud clock generator |
Generates the transmitter and receiver baud clock. With a reference clock of 100 MHz, the UART controller supports transfer rates of 95 baud to 6.25 Mbaud. This supports communication with all known 16550 devices. The baud rate is controlled by programming the interrupt enable or divisor latch high (IER_DLH) and receive buffer, transmit holding, or divisor latch low (RBR_THR_DLL)registers |
Serial transmitter |
Converts parallel data written to the UART into serial data and adds all additional bits, as specified by the control register, for transmission. This makeup of serial data, referred to as a character, exits the block in serial UART. |
Serial receiver |
Converts the serial data character (as specified by the control register) received in the UART format to parallel form. Parity error detection, framing error detection and line break detection is carried out in this block. |
DMA interface |
The UART controller includes a DMA controller interface to indicate when received data is available or when the transmit FIFO buffer requires data. The DMA requires two channels, one for transmit and one for receive. The UART controller supports single and burst transfers. You can use DMA in FIFO buffer and non-FIFO buffer mode |