Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.1.6.12.1. Clock Domain

Depending on the interface, you use the following different clock domains:
  • When the DMA host interface is used for EMAC packet transfers, the l4_main_clk is used as a clock source for AXI manager for the DMA data transaction and l4_sp_clk is used as clock source for the APB agent DMA CSR register interface.
  • The RX and TX FIFO RAMs are driven by the l4_mp_clk.
  • The MDIO interface's clock domain is derived from the CSR clock, which comes from the l4_sp_clk. The typical MDC clock has a frequency between 1 to 2.5 MHz.
  • The EMAC contains a RX datapath, a TX datapath and timestamp interface that all run on separate clock domains:
    • The RX datapath is in the EMAC RX clock domain (clk_rx_312pt5_i).
    • The TX datapath is in the EMAC TX clock domain (clk_tx_312pt5_i).
    • The timestamp interface is in the PTP reference clock domain (clk_ptp_ref).
A block diagram of the EMAC clock domains is shown in the following figure.
Figure 84. EMAC Clock Domains
Table 165.  EMAC Clock Details
Clock Input/Output Frequency Source Description
l4_main_clk Input 400 Mhz Clock manager Application clock for AXI DMA bus interface, act as primary clock for EMAC to interconnect
l4_sp_clk Input 100 MHz Clock manager Clock source for APB CSR interface.
l4_mp_clk Input 250 MHz Clock manager Clock source for EMAC RX read interface and TX FIFO write interface.
emac_ptp_clk_clk Input 400 MHz Clock manager

The timestamp domain clock is sourced from the clock manager. The source can be selected through the emacptpen, either from the PLLs or from the FPGA.

The source can be selected through the ptp_clk_sel bit of the tsn_global register in the system manager module. When the bit is clear, the emac_ptp_clk is selected and when it is set, the f2h_ptp_ref_clk is selected.

emac*_clk Input

Variable depending on divider value of programmed in clock manager.

Input from clock manager This signal is configured in the clock manager module and can be enabled to drive the clk_tx_int and clk_rx_int signals to the TX and RX clock domains.
phy_clk_tx_i Input Used only at lower speed of GMII mode - 10/100 Mbps speed mode as a 2.5 or 25 MHz clock respectively Input from FPGA fabric I/O
This signal is used only when HPS EMAC is exported to FPGA fabric as GMII interface as a TX reference clock.
Note: This clock must be able to perform glitch free switching between 2.5 and 25 MHz.
phy_clk_rx_i Input
  • GMII mode:315.5, 125, 25, or 2.5 Mhz
  • RGMII mode: 125, 25, or 2.5 MHz

This clock input is driven to the FPGA or by an HPS I/O input from an external PHY

This clock signal is the RX PHY input clock.

These datapath clocks are:

  • 312.5 MHz when operating in 2.5 Gbps - mode
  • 125 MHz when operating in 1 Gbps mode
  • 25 MHz when operating in 100 Mbps - mode
  • 2.5 MHz when operating in 10 Mbps mode
phy_txclk_o Output 312.5, 125, 25, or 2.5 MHz

This clock is sourced from the FPGA fabric (phy_clk_tx_i) and it is only made available when HPS EMAC is exported to FPGA fabric as GMII interface.

This signal is the EMAC GMII GTX output clock to the PHY.

Clock Diagram

The following figure shows the top-level EMAC clock diagram.
Figure 85. EMAC Clock Diagram
Table 166.  EMAC Interface and Datapath Source Clock
System Manager Datapath Source Clock
phy_intf_sel[1:0] RX Datapath (clk_rx_int) TX Datapath (clk_tx_int) phy_txclk_o 20
GMII 21 FPGA fabric (phy_clk_rx_i) FPGA fabric (phy_clk_tx_i) FPGA fabric (phy_clk_tx_i)
RGMII FPGA fabric (phy_clk_rx_i) Clock Manager (clk_ref_i) Not used
RESET Clock Manager (clk_ref_i) Clock Manager (clk_ref_i) Not used
20 phy_txclk_o is the GMII GTX clock output when HPS is exported to FPGA fabric as GMII interface
21 In GMII mode:
  • For 10/100M speed mode, the transmit data synchronous TX clock is generated from PHY to MAC. phy_clk_tx_i is sourced from FPGA fabric (PHY).
  • For 1/2.5G speed mode, transmit data synchronous TX clock is generated from MAC to PHY. phy_txclk_o is sourced from clock manager (MAC).
  • phy_txclk_i and phy_clk_tx_o are synchronous through the same source clock.