Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

7.6.5.2. XGMAC Clocks

The following table shows the clock information for the XGMAC clocks.

Table 298.  XGMAC Clocks
Clock Name XGMAC Wrapper Clock Name Source Destination Description
l4_main_clk clk_app_i Clock manager AXI manager interface Primary clock for XGMAC interface to interconnect
l4_sp_clk clk_csr_i Clock manager CSR interface Clock for XGMAC register access
emac_ptp_clk clk_ptp_ref_i Clock manager PTP Timestamp PTP clock reference
clk_rx_312pt5_i clk_rx_int XGMAC CLKGEN XGMAC XGMAC receiver clock
clk_tx_312pt5_i clk_tx_int XGMAC CLKGEN XGMAC XGMAC transmitter clock
phy_txclk_o phy_txclk_o XGMAC CLKGEN HPS IO / Fabric Transmit clock to HPS I/O and Fabric

The XGMAC mode of operation is determined by a combination of the system manager phy_intf_sel[1:0] output and the ethernet SS[2:0] output as defined in the following table. Table cells list the CLKGEN input or derivation of an input that is required to generate the output listed in the column heading.

Any lines where there is a “not supported” comment or “----” in a table cell can be treated as a "don’t care".

Table 299.  XGMAC Modes of Operation
phy_intf_sel [1:0] 29 mac_speed_o [2:0] 30 Mode

clk_ref_i

(Clk Mgr output)

clk_tx_int

(XGMAC Xmit Clk output)

clk_rx_int

(XGMAC Rcv Clk output)

phy_txclk_o

(PHY Xmit Clk output)
Notes

‘b00

(GMII)

‘b000 10G XGMII ---- ---- ---- ---- Not supported
‘b001 Reserved ---- ---- ---- ---- Not supported
‘b010 2.5G GMII ----

phy_clk_tx_i

(fabric via pinmux)

phy_clk_rx_i

(fabric via pinmux)

----
‘b011 1G GMII 250 MHz clk_ref_i/2

phy_clk_rx_i

(fabric via pinmux)

clk_tx_int
‘b100 100M GMII ----

phy_clk_tx_i

(fabric via pinmux)

phy_clk_rx_i

(fabric via pinmux)

clk_tx_int
‘b101

5G

XGMII

---- ---- ---- ---- Not supported
‘b110

2.5G

XGMII

---- ---- ---- ---- Not supported
‘b111 10M GMII ----

phy_clk_tx_i

(fabric via pinmux)

phy_clk_rx_i

(fabric via pinmux)

clk_tx_int

‘b01

(RGMII)

‘b000 N/A ---- ---- ---- ---- Speed not supported by RGMII.
‘b001 Reserved ---- ---- ---- ----

Not supported by XGMAC IP.

‘b010 N/A ---- ---- ---- ----

Speed not supported by RGMII.

‘b011

1G

RGMII

250MHz clk_ref_i/2

phy_clk_rx_i

(I/O via pinmux)

tx_clk_int
‘b100

100M

RGMII

250MHz clk_ref_i/10

phy_clk_rx_i

(I/O via pinmux)

clk_tx_int
‘b101 N/A ---- ---- ---- ----

Speed not supported by RGMII.

‘b110 N/A ---- ---- ---- ----

Speed not supported by RGMII.

‘b111

10M

RGMII

250MHz clk_ref_i/100

phy_clk_rx_i

(I/O via pinmux)

clk_tx_int

‘b10

(RMII-unsupported)

‘bxxx N/A ---- ---- ---- ---- Not supported

‘b11

(Reset)

‘bxxx Reset 250MHz clk_ref_i/2 clk_ref_i/2 ----

Default to provide clocks to XGMAC before mode is selected.

29 The full register name is System_Mgr.tsn<n>.phy_intf_sel[1:0], where <n> = <0,1,2>
30 The full register name is <n>EMAC<n>_DWCXG_CORE.MAC_Tx_Configuration.SS[2:0], where <n> = <0,1,2>