Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

4.1.1. CCU Differences Among Intel SoC Device Families

The following table shows how cache coherency unit is implemented among the Intel SoC device families.

Table 61.  CCU Differences Among Intel SoC Device Families
Feature

Cyclone® V SoC,

Arria® V SoC

Arria® 10 SoC

Stratix® 10 SoC

Intel® Agilex™ 7

F-Series/I-Series/

M-Series SoC

Agilex™ 5

E-Series/D-Series SoC

Cache coherency unit Implemented by ACP in MPCore and ACP ID mapper block Implemented by ACP in MPCore and level 3 (L3) interconnect Implemented by cache coherency unit (CCU) based on Netspeed Gemini IP Implemented by cache coherency unit (CCU) based on Arteris Ncore2 IP Implemented by cache coherency unit (CCU) based on Arteris Ncore3 IP

Cyclone® V SoC, Arria® V, and Arria® 10 SoC devices implement system level cache coherency by exposing the MPU accelerator coherency port (ACP) to initiators in the system including the FPGA fabric connected to the FPGA-to-HPS bridge. The Cyclone® V and Arria® V SoCs require these initiators to access the ACP ID mapper while Arria® 10 SoC only requires the initiators to perform cacheable accesses to the MPU cache subsystem.

The Stratix® 10 HPS includes a cache coherency unit that resides between the MPU and the rest of the system, allowing cacheable accesses from initiators in the system, including soft IP in the FPGA fabric connected to the FPGA-to-HPS bridge. The Stratix® 10 HPS CCU also performs routing functionality between the MPU, FPGA-to-HPS bridge, L3 interconnect, and SDRAM. Stratix® 10 SoC CCU is based on the Netspeed Gemini interconnect IP.

The Intel® Agilex™ 7 CCU is similar with the Stratix® 10 CCU, but it is based on the Arteris Ncore2 interconnect IP.

The Agilex™ 5 CCU is similar with the Intel® Agilex™ 7 CCU, but it is based on the new Arteris Ncore3 interconnect IP. This IP is designed from the ground up to support the CHI-B protocol that the DSU uses in place of ACE.

The AxPROT[0] tunnelling supported on Intel® Agilex™ 7 does not apply to Agilex™ 5.