Visible to Intel only — GUID: yvf1679501757450
Ixiasoft
Visible to Intel only — GUID: yvf1679501757450
Ixiasoft
5.8.6.6.9. Master Request Generation
The I3C controller can generate the Master Request (MR) in non-current master mode to request for I3C bus ownership from the current master.
The application of the I3C controller can decide to send a Master Request by asserting the MR bit in the Slave Interrupt Request register.
The status of the IBI generation is updated in the IBI_STS field of Slave Interrupt Request register (SLV_INTR_REQ), which is informed to the application by the IBI_UPDATED_STS interrupt in INTR_STATUS register by I3C controller. Also after IBI_STS is updated, the MR bit in SLV_INTR_REQ register is auto cleared. On receiving this interrupt, the slave application can read the IBI_STS field in the Slave Interrupt Request register.
IBI_STS | Value | Description |
---|---|---|
Reserved | 00 | Default value |
Success | 01 | MR accepted by the master (ACK response received). |
Reserved | 10 | Reserved |
Not Attempted | 11 | MR not attempted |
The controller does not attempt to issue the IBI and generates the Not Attempted (2'b11) status under the following conditions.
- Master has not assigned the dynamic address.
- Master has cleared the assigned dynamic address through RSTDAA.
- Master has disabled the MR_EN through DISEC CCC (MR_EN in SLV_EVENT_STATUS register).
- The controller has switched the role to master (applicable only for secondary master configuration).
The following are the SIR-related registers for the I3C controller. For more information, refer to the Address Map
- IBI_UPDATED_STAT
- SLV_INTR_REQ
- SLV_EVENT_STATUS
- BUS_FREE_AVAIL_TIMING