Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

7.6.7. SD/eMMC, NAND, and SoftPHY/ComboPHY

The following diagram shows the SD/eMMC, NAND, and SoftPHY/ComboPHY block diagram.

Figure 263. SD/eMMC, NAND, and SoftPHY/ComboPHY Block Diagram

The following table provides information for the NAND, SD, and eMMC memory types.

Table 302.  Mode, Speed, and Controller Frequency Detail by Memory Type
Memory Type Mode Speeds Controller Frequency
NAND SDR Asynchronous 50 MHz
NV-DDR 200 MT/s 100 MHz
NV-DDR2 Up to 200 MT/s 100 MHz
SD SDR12 12.5 MB/s

50 MHz 31

SDR25 25 MB/s 50 MHz
SDR50 50 MB/s 100 MHz
SDR104

100 MB/s 32

200 MHz
DDR50 50 MB/s 50 MHz
eMMC Legacy Up to 25 MB/s

50 MHz31

High Speed SDR Up to 50 MB/s 50 MHz
High Speed DDR Up to 100 MB/s 100 MHz
HS200 (SDR) 200 MB/s 200 MHz
HS400 (DDR) 400 MB/s 200 MHz

The following tables provide descriptions for the NAND, SD/eMMC, and SoftPHY clock signals.

Table 303.  NAND Clock Signals
NAND Clock Signal Description
regPCLK Clock for NAND Flash controller register access from system interconnect
mACLK NAND Flash controller global clock
nf_clk The clock signal for NAND Flash clock domain
phy_reg_pclk Clock for NAND Flash controller access to softPHY APB interface
bch_clk The clock signal for BCH engine clock domain
Table 304.  SD/eMMC Clock Signals
SD/eMMC Clock Signal Description
s_pclk Clock for SD/eMMC controller register access from system interconnect
clk SD/eMMC controller global clock
sdmclk The clock signal for SD/eMMC Flash clock domain
sdphy_reg_pclk Clock for SD/eMMC controller access to softPHY APB interface
Table 305.  SoftPHY Clock Signals
SoftPHY Clock Signal Description
clk_phy This is the main PHY clock signal. The frequency of this clock needs to be compliant with the NAND or SD/eMMC device work mode. The maximum frequency for this clock is based on the ONFI4.1 specification
clk_ctl For the NAND Flash controller, the frequency of this clock signal is ½ the frequency of clk_phy. For SD/eMMC, a 1:1 clock ratio to clk_phy is supported. All signals on the DFI interface between the controller and PHY are synchronous with this clock.
reg_pclk Clock for NAND or SD/eMMC controller access to softPHY APB interface

The following table shows the registers used to program the clocks.

Table 306.  Programming Clock Registers
Clock Name *.src *.cnt (n+1 divider) *.div (2^n divider) Clock Gate (enable)
l4_mp_clk

mainpllgrp.nocclk.src

= 0 (Main_PLL_C3)

= 1 (Peri_PLL_C1)

--- mainpllgrp.nocdiv.l4mpclk mainpllgrp.en.l4mpclken
SD/eMMC / NAND / SoftPHY

SoftPHY:

phy_clk

l4_mp_clk --- mainpllgrp.nocdiv.softphydiv ---

SoftPHY:

dfi_clk

phy_clk ---

System_Mgr.dfi_interface_cfg.dfi_ctrl_sel 33

---

SD/eMMC:

sdphy_reg_clk, S_pclk, clk

l4_mp_clk --- --- perpllgrp.en.sdmmcclken

SD/eMMC:

sdmclk

dfi_clk --- ---

NAND:

bch_clk, mACLK, regPCLK, phy_reg_pclk

l4_mp_clk --- --- perpllgrp.en.nandclken

NAND:

nf_clk

dfi_clk --- ---

SoftPHY:

clk_ctrl

dfi_clk --- --- perpllgrp.en.softphyclken

SoftPHY:

clk_phy

phy_clk --- ---

SoftPHY:

reg_pclk

l4_mp_clk --- ---
31 The clock to the SD card will be the controller clock divided by two in these cases, and by 1 in all other cases.
32 To obtain the 104 MB/s, a controller clock of 208 MHz would be needed. With a maximum clock of 200 MHz, only 100MB/s can be obtained
33 System_Mgr.dfi_interface_cfg.dfi_ctrl_sel. If using NAND, then set this to =0. If using SD/eMMC, then set this to =1.