Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

4.3.4.1. TBU Instances

The SMMU contains six instances of the TBU as shown in the following table.

Table 82.   TBU Instances

Instance

Partition

Connected components

DMA_TBU

PSS

DMA0, DMA1 controllers

SDM_TBU

PSS

SDM

IO_TBU

PSS

USB2.0 OTG, USB3.1, ETR, SD/eMMC, NAND

TSN_TBU

PSS

EMAC (TSN)

F2H_TBU

APS

FPGA Fabric traffic going to the HPS

F2SDRAM_TBU

MPFE

FPGA Fabric traffic going to memory

There are four different configurations of the TBU. The DMA_TBU, SDM_TBU, and IO_TBU all share the same configuration. The TSN_TBU has a slightly different configuration from the TBUs connected to the other IO devices because the EMAC (TSN) is more sensitive to performance. The two TBUs that are connected to the FPGA fabric are also unique. Specifically, they have a much wider data interface.