Visible to Intel only — GUID: hqa1677601243803
Ixiasoft
Visible to Intel only — GUID: hqa1677601243803
Ixiasoft
4.1.2. CCU Use Cases
The main use case for CCU is to support a system where an accelerator implemented in soft logic shares data with either the Cortex-A55 or the Cortex-A76 cores or both in the DSU. An example is a EMAC (TSN) endpoint as shown in the following diagram.
In such a system, the CPU(s) must be notified when soft logic is about to update shared data so that the L1, L2, and L3 caches can invalidate any clean cache lines associated with the new data or write any dirty lines back to main memory. Similarly, any read performed by the soft logic accelerator must return the latest copy of data whether it is located in main memory or one of the previously stated caches. It is the job of CCU to ensure that every transaction initiator shares a common view of main memory, even if the latest data is not resident in main memory. The CCU does this by maintaining a directory of all the cache lines that are resident in the L3 cache so that the proper cache maintenance commands can be issued when needed. This eliminates the requirement for cache maintenance software, and thus improves system performance.