Visible to Intel only — GUID: neb1677724901063
Ixiasoft
Visible to Intel only — GUID: neb1677724901063
Ixiasoft
13.4.3. Transaction Privilege
The system interconnect supports two levels of privilege: privileged (or supervisor), non-privileged (or user) for a transaction. Privilege is supported for all initiators on the system interconnect. Privilege is enforced only on writes. A write from a non-privileged initiator to a privileged target results in an error. Reads have no privilege requirement.
The table below shows how the privilege state of a target is used with the transaction privilege bit to determine if a transaction passes or fails.
Transaction Privilege Bit | Target Privilege State | Result |
---|---|---|
Non-Privileged | Privileged | Fail |
Privileged | Privileged | Pass – transaction sent to target |
Non-Privileged | Non-Privileged | Pass – transaction sent to target |
Privileged | Non-Privileged | Pass – transaction sent to target |
AXI supports privilege via A*PROT[0] bit and other bus protocols may also have equivalents.
The following table shows the details for the initiator privilege level.
Initiator | Privilege Bit | Privileged State | Non-Privileged State | Source |
---|---|---|---|---|
AXI-AP | A*PROT[0] | 1 | 0 | Driven by AXI-AP |
CCU_IOS | A*PROT[0] | 1 | 0 | Driven by CCU (transported from MPU and FPGA2HPS) |
DMAx | A*PROT[0] | 1 | 0 | Driven by DMA |
EMACx (TSNx) | A*PROT[0] | 1 | 0 | Driven by system manager |
EMAC_TBU | A*PROT[0] | 1 | 0 | Driven by TBU (transported from EMAC/TSN or page table attribute) |
ETR | A*PROT[0] | 1 | 0 | Driven by ETR |
ETR_TBU | A*PROT[0] | 1 | 0 | Driven by TBU (transported from ETR or page table attribute) |
NAND | A*PROT[0] | 1 | 0 | Driven by system manager |
SD/eMMC | A*PROT[0] | 1 | 0 | Driven by system manager |
USB3.x | A*PROT[0] | 1 | 0 | Driven by system manager |
USB2.x | H*PROT[0] | 1 | 0 | Driven by system manager |
IO_TBU | A*PROT[0] | 1 | 0 | Driven by TBU (transported or page table attribute) |
SDM2HPS_LL | A*PROT[0] | 1 | 0 | Driven by PSI |
SDM2HPS_BE | A*PROT[0] | 1 | 0 | Driven by PSI |
SDM_TBU | A*PROT[0] | 1 | 0 | Driven by TBU (transported from PSI or page table attribute) |
The following table shows the details for the target privilege level.
Target Socket | Privilege Level | Programmable | Enforced By |
---|---|---|---|
L4_AHB | Privileged | Yes | NOC |
L4_MAIN | Privileged | Yes | NOC |
L4_MP | Privileged | Yes | NOC |
L4_SP | Privileged | Yes | NOC |
L4_ECC | Privileged59 | No | Target |
L4_SEC | Privileged60 | No | Target61 |
L4_SHR | Privileged62 | No | Target |
L4_SYS | Privileged | No | NOC |
L4_SYS_GENTS (generic timestamp) |
Privileged | Yes | NOC |
TCU_s | Privileged | Yes | NOC |
CCU_IOM | Non-privileged | No | None |
APB-DAP | Non-privileged | No | None |
HPS2SDM_LL|BE | Non-privileged | No | None |
L4_NOC | Privileged | No | NOC |
LWHPS2FPGA | Privileged | Yes | NOC |
HPS2FPGA | Privileged | Yes | NOC |
STM | Non-privileged | No | None |