Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public

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Document Table of Contents

5.1.6.2.7. DMA Descriptor Write-Back Operation

The DMA descriptor write-back operation is triggered when the descriptor is passed to it by the data transfer engine after the corresponding buffer contents are transferred. This engine closes the descriptor with OWN bit = 0 to indicate to the software that the descriptor is freed-up.

For TxDMA, the descriptor write-back operation clears the TDES3 field while the other TDES0-TDES2 fields are not modified. This write-back request is issued independently of the buffer data transfer requests (pointed by the next descriptor) by the TxDMA engine.

For RxDMA, the descriptor is closed with the status fields also updated in RDES0-RDES3 fields. To ensure that the buffer transfer to system memory is complete before the descriptor is closed, these transfer operations are performed in sequence with the same AXI ID. In other words, the RxDMA engine starts performing the next descriptor's buffer transfer only after the current descriptor is written back and closed. This sequencing is done to ensure that the software does not process the descriptor and read the buffer contents before the buffer data transfers are completed by the hardware.

The transfer complete interrupts TI (bit[0]) in case of TxDMA and RI (bit[6]) in the case of RxDMA is generated when the descriptor corresponding to the last segment of the packet data is closed and also has the Interrupt On Completion bit set. The interrupt is generated only after the response to the descriptor write transfer is received from the target.

If the interrupt generation is not enabled for that packet, the descriptor write operation is deemed to be completed once the descriptor write request is accepted by the target (without waiting for the response from the target). This reduces the latency of descriptor write completion and improves the throughput.