Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

A.3.4. Configuration Bitstream

The configuration bitstream is broadly organized into sections: the SDM firmware section and one or more design data sections. The SDM boots the SDM firmware, which sets up the SDM hardware to apply the configuration bitstream security policies and load the design data sections. This includes FPGA core configuration, FPGA I/O configuration, a partial reconfiguration (PR) persona, or HPS first stage boot loader (FSBL).

After the SDM completes device configuration, it is available to process commands received via a mailbox interface, respond to reset or reconfiguration events, or provide security services to FPGA logic and HPS software.