Visible to Intel only — GUID: ecz1678585736373
Ixiasoft
Visible to Intel only — GUID: ecz1678585736373
Ixiasoft
5.7.5.8.1. Reset Requirements
There must be a minimum of 12 cycles on the ulpi_clk clock before the controller is taken out of reset. During reset, the USB OTG controller asserts the ulpi_stp signal. The PHY outputs a clock when it sees the ulpi_stp signal asserted. However, if the pin multiplexers are not programmed, the PHY does not see the ulpi_stp signal. As a result, the ulpi_clk clock signal does not arrive at the USB OTG controller.
Software must ensure that the reset is active for a minimum of two l4_mp_clk cycles. There is no maximum assertion time.