Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

8.6.2.3. HPS Idle Sequence

The HPS enters the HPS idle sequence when it is in normal operation, and a cold, warm, or watchdog reset request is received.

The following diagram shows the steps in the HPS idle sequence.

Figure 272. HPS Idle Sequence

The HPS Idle sequence will have access to fence and drain logic on all incoming and outgoing ports. If enabled, fence and drain shall be performed on the associated port and a timeout counter shall be started. The state machine shall proceed to the Reset Assertion sequence when all enabled ports either complete fence and drain successfully or timeout is reached.

Note: Fence and drain of the PSI will be masked if a cold reset is requested. This is because the SDM firmware has already put the PSI link in a quiescent state before requesting a cold reset.
Note: The F2H and F2SDRAM bridges are updated with a state machine that fences and drains both the bridge and the associated MPFE/CCU NIUs by using the existing F2H and F2SDRAM handshakes from the reset manager. Once these two paths are cleared of outstanding transactions, the reset manager then fences and drains the CCU to MPFE ports, to ensure all traffic to the SDRAM is cleared.