Visible to Intel only — GUID: zfo1675715011695
Ixiasoft
Visible to Intel only — GUID: zfo1675715011695
Ixiasoft
8.6.2.3. HPS Idle Sequence
The HPS enters the HPS idle sequence when it is in normal operation, and a cold, warm, or watchdog reset request is received.
The following diagram shows the steps in the HPS idle sequence.
The HPS Idle sequence will have access to fence and drain logic on all incoming and outgoing ports. If enabled, fence and drain shall be performed on the associated port and a timeout counter shall be started. The state machine shall proceed to the Reset Assertion sequence when all enabled ports either complete fence and drain successfully or timeout is reached.