Visible to Intel only — GUID: qnq1673393440796
Ixiasoft
Visible to Intel only — GUID: qnq1673393440796
Ixiasoft
5.1.6.2. DMA Controller
The DMA has independent Transmit (TX) and Receive (RX) engines, and a CSR space. The TX engine transfers data from the system memory to the device port or MAC Transaction Layer (MTL), whereas the RX engine transfers data from the device port to the system memory. The controller uses descriptors to efficiently move data from source to destination with minimal application CPU intervention. The DMA is designed for packet-oriented data transfers such as packets in Ethernet. The controller can be programmed to interrupt the application CPU for situations such as packet transmit and receive transfer completion, and other normal or error conditions.
- Control and status registers (CSR)
- Descriptor lists and data buffers
The DMA transfers the data packets received by the MAC to the RX buffer in system memory and TX data packets from the TX buffer in the system memory. The descriptors that reside in the system memory contain the pointers to these buffers.
The DMA supports up to 16 TX and 16 RX descriptor lists (or DMA channels). The base address of each list is written to the respective TX descriptor list address register and RX descriptor list address register. The descriptor list is forward linked and the next descriptor is always considered at a fixed offset to the current one. The offset is controlled by the programming of the DSL field of DMA_Ch(#i)_Control register. The number of descriptors in the list is programmed in the respective TX (or RX) descriptor ring length register. After the DMA processes the last descriptor in the list, it jumps back to the descriptor in the list address register to create a descriptor ring.
- When the EMAC is configured with an address greater than 32 bits, the DMA considers that all the descriptors in a list are present in a memory page with maximum size of 4 GB. In other words, address bits greater than 32 are taken to be constant and equal for all the descriptors in the ring. However, the upper bits of the various buffer addresses can be different and independent.
- When the EMAC is configured with an address greater than 32 bits, the TX descriptor can have only one buffer address. However, the RX descriptor can still have two buffer addresses.
A data buffer resides in the application physical memory space and consists of an entire packet or part of a packet but cannot exceed a single packet. Buffers contain only data. Buffer status is maintained in the descriptor. Data chaining refers to packets that span multiple data buffers. However, a single descriptor cannot span multiple packets. The DMA skips to the data buffer of next packet when EOP is detected.
The EMAC supports the ring structure for the DMA descriptor. Refer to Descriptor Overview for details about descriptor structure and how the DMA accesses the descriptors.
- Multiple descriptor fetch
- Data transfer
- Descriptor write-back
- In case of the RX DMA, the data transfer phase and descriptor write-back phase cannot be made totally independent, since the order of the data transfer and descriptor write-back has to be strictly followed for maintaining synchronization between the software processing of descriptors and the packet transfers. This ensures that the software processes the closed descriptors only after the corresponding packet buffer is transferred and written into system memory.
- When the DSPW bit in the DMA_Mode register is set, the descriptor writes are made as posted writes. EMAC does not wait for the write response from the target to take further actions. This makes the interrupt generation based on the IOC bit in the descriptor unreliable. Therefore, when DSPW is set, the IOC bit in the RX descriptor must not be set.
Section Content
Application Bus Burst Access
Application Data Buffer Alignment
Buffer Size Calculations
DMA Descriptor Fetch Operation
DMA TX Data Transfer Operation
DMA RX Data Transfer Operation
DMA Descriptor Write-Back Operation
DMA Start/Stop Operation
Memory Cache Size Requirements
Memory Cache Access Arbitration
DMA Error Handling