Visible to Intel only — GUID: oii1674595403843
Ixiasoft
Visible to Intel only — GUID: oii1674595403843
Ixiasoft
7.2.1. A76 Core Power and Performance Trade-off
The operating frequency of each of the two A76 cores is independently controllable via software, allowing you to make the optimum power and performance trade-off for your application. If you need A55 core class performance from an A76 core, you can program a ping-pong counter to divide the PLL clock down to an appropriate frequency. If you need maximum A76 core performance, you can program the ping-pong counter to divide by 1.
Software updates to ping-pong counter dividers have seamless transitions on output clocks. Therefore, software can dynamically change the frequency by changing the ping-pong counter value (integer divider), however, the input to the ping-pong counters cannot be changed dynamically.
The presence of independent, software-controllable ping-pong counters provides the opportunity for you to perform dynamic power management using your own software algorithms.
A software-controllable clock gate is provided for each A76 core to allow you to disable clocks when a CPU is powered but not in use. Dynamic clock gating is not supported.