Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.3.5.1. Device Discovery Interface

The signals described in this section are the most important signals that belong to the device discovery interface and their value can be set or accessed from the system manager registers. The values in these signals are used during the device discovery process. For some of the signals, the values on them are used only to provide a default value during the device discovery mechanism, while in some other signals, their values are propagated to the NAND Flash controller and Combo PHY registers. Also, some other signals propagate from the NAND Flash controller to the system manager, and these can be read as status signals in the system manager registers.

Table 178.  Device Discovery Interface Signals
NAND Flash Controller Signal Direction to NAND Flash Controller Description
discovery_inhibit Input Bootstrap port stops controller from initialization. Controller will not start device discovery process. This signal must be stable and have proper value by the time the controller comes out of reset.
discovery_ignore_crc

Input

When tied to 1, the controller ignores CRC checking after reading parameter page during device discovery process.
rb_valid_time

Input

PHY initialization parameter for device discovery process.

Calculate the value of this parameter as: RB_VALID_TIME = Trb[us] * fsys [MHz], where:

Trb: value of the RB_valid_Vcc time (from NAND Flash device specification).

fsys: frequency of the system clock (200 MHz).

phy_*_reg Input

If the NAND Flash device starts in toggle work mode, set these signals to the correct value in the system manager module. The values in these registers are propagated as input signals to the NAND Flash controller, and this uses them to configure the corresponding PHY registers after completing the device discovery process.

In ONFI mode, these values come from the parameter page.

dd_pages_per_block Input

Device discovery external parameters - number of pages in single block.

dd_page_size Input

Device discovery external parameters - number of bytes in single NAND Flash page.

dd_ack Input

Device discovery external parameters acknowledge signal.

dd_lun_number Input

Device discovery external parameters - number of LUNs in single NAND Flash device.

dd_row_addr_width Input

Device discovery external parameters - number of row address cycles. Port encoding is as follows:

2'b00 - three bytes row address

2'b01 - two bytes row address

2'b10 - four bytes row address

dd_support_16_bit Input

Device discovery external parameters - 16-bit NAND Flash device connected.

dd_id_value Output ReadID value read from NAND flash device.
dd_req Output Device discovery status register. External parameters request.
init_comp Output Initialization complete. When device discovery process is finished this bit will be set.
init_fail Output Initialization fail (valid when init_comp =1).
ctrl_busy Output

Signal indicating if the NAND Flash controller is idle or not

1 - Controller is busy

0 - Controller is idle

This signal can be used by host for active clock management to controller.