Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

8.5.2. HPS Reset Domain to Signal Mapping

The following table shows the reset signals which are part of each reset domain. The shaded cells indicate the reset type (POR, cold, warm, debug, bridge and CPU) where the reset manager asserts the associated reset signal.

Table 327.  HPS Reset Domain to Signal Mapping
Domain Module Reset Signal POR Cold Warm Debug Comment
POR por_rst_n       POR reset for all of HPS (both HPS and FPGA power is good).
SYSCFG sys_config_rst_n

System configuration cold and warm reset for all modules accessible by SDM.

SYSCFG NOC is connected to this signal.

serial_ctrl_rst_n

Serial controller reset. Needs to be separate from reset manager for warm reset request handshake.

Externally triggered reset from secure manager serial controller reset register bit.

SYSCFG Cold sys_config_cold_rst_n System config cold reset only to system manager, reset manager, and IO manager (pinmux).
nPERIPHRESET DSU reset for all logic in the PERIPHCLK domain.
DSU nPRESET DSU reset for logic in the PCLK domain which included debug and the debug APB interface.
DSU nATRESET DSU reset for logic in the ATCLK domain which include the ATB trace bus.
nSPORESET DSU reset for all logic in the SCLK domain including RAS registers.
L3 l3_rst_n   Reset for PSS NOC, CCU, and MPFE (except for IO Bank target NIUs)
emif_rst_n √*

Reset for MPFE target NIUs to IO Bank and MPFE-lite. Allows for SW reset of those ports.

√* = Asserted if warm reset mask clear. SW negates.

H2F h2f_reset       Indicates that the HPS is in warm reset
h2f_cold_reset     Indicates that the HPS is in cold reset
h2f_watchdog_reset   Indicates that a Watchdog reset was triggered

h2f_warm_reset_handshake_n

(h2f_warm_reset_handshake_reset_req_n, h2f_warm_reset_handshake_reset_ack_n)

  Handshaking mechanism between the HPS and the FPGA during an HPS warm reset
Debug dbg_rst_n Debug domain reset. Includes CoreSight and trace outside of DSU
cs_at_reset ATB reset
cs_dap_rst_n Debug peripheral reset
Debug Block nPRESET DSU debug block (outside of DSU) reset
COREx Warm nCORERESET[3:0]

COREx warm reset, does not include debug logic

COREx Cold nCPUPORESET[3:0] COREx cold reset including debug logic
L2 nSRESET DSU reset for all logic in the SCLK domain except for RAS registers
nGICRESET DSU reset for all logic in the GICCLK domain
FPER dma_rst_n SW negates.
dma_ecc_rst_n SW negates.
dma_periph_if_rst_n[7:0] SW negates.
spim_rst_n[1:0] SW negates.
spis_rst_n[1:0] SW negates.
PER emac_rst_n[2:0]   SW negates.
usb_rst_n[1:0]

SW negates.

usb_rst_n[0] = USB2OTG reset.

usb_rst_n[1] = USB3.1 reset.

nand_flash_rst_n SW negates.
sdmmc_rst_n SW negates.
softphy_rst_n SW negates.
emac_ecc_rst_n[2:0] SW negates.
usb_ ecc_rst_n[1:0] SW negates.
nand_flash_ecc_rst_n SW negates.
sdmmc_ecc_rst_n SW negates.
emac_ptp_rst_n SW negates.
i3c_rst_n[1:0] SW negates.
SPER watchdog_rst_n[3:0]   SW negates.
l4sys_timer_rst_n[1:0] SW negates.
sp_timer_rst_n[1:0] SW negates.
i2c_rst_n[2:0] SW negates.
uart_rst_n[1:0] SW negates.
gpio_rst_n[1:0] SW negates.
BRG hps2fpga_axi_reset √*
√* = Asserted if warm reset mask clear. SW negates.
Note: Must be connected to h2f_reset.
lwhps2fpga_axi_reset √*
√* = Asserted if warm reset mask clear. SW negates.
Note: Must be connected to h2f_reset.
fpga2hps_reset √*
√* = Asserted if warm reset mask clear. SW negates.
Note: Must be connected to h2f_reset.
f2sdram_axi_reset √*
√* = Asserted if warm reset mask clear. SW negates.
Note: Must be connected to h2f_reset.
TAP tap_rst_n Asserted with POR