Visible to Intel only — GUID: tiu1674505908534
Ixiasoft
Visible to Intel only — GUID: tiu1674505908534
Ixiasoft
9.3.1. DSU L3 Cache Power Gating
The DSU L3 cache has a total size of 2 MB. When the full L3 cache capacity is not required, the L3 cache size can be reduced to half (1 MB) by powering down portions of the cache which reduces RAM leakage power. The L3 memory is configured as dual slice mode as shown in the diagram below.
In the case of dual slice mode, the overall cache is effectively divided into two. Each cache slice has its own associated logic, but they are not independent. For each cache slice, the data RAM is subdivided into two portions, while the tag RAM is subdivided into four portions. Power control can be applied independently to each portion. The operating cache capacity can be selected from: All ON, ½, or None.