Visible to Intel only — GUID: psd1672444548494
Ixiasoft
1. Agilex™ 5 Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
3. Micro Processor Unit (MPU)
4. Application Processor Subsystem
5. Peripheral Subsystem
6. System Manager
7. Clock Manager
8. Reset Manager
9. Power Management
10. Address Map
11. Bridges
12. Interfaces
13. System Interconnect and Firewalls
14. Error Checking and Correction Controller
15. CoreSight Debug and Trace
16. HPS Register Map
A. Appendix
1.1. Introduction to the HPS Revision History
1.2. MPU Revision History
1.3. CCU Revision History
1.4. GIC Revision History
1.5. SMMU Revision History
1.6. On-Chip RAM Revision History
1.7. EMAC Revision History
1.8. DMA Controller Revision History
1.9. NAND Flash Controller Revision History
1.10. SD/eMMC Revision History
1.11. Combo DLL PHY Revision History
1.12. USB 3.1 Gen1 Controller Revision History
1.13. USB 2.0 OTG Controller Revision History
1.14. I3C Controller Revision History
1.15. I2C Controller Revision History
1.16. SPI Controller Revision History
1.17. Timers Revision History
1.18. Watchdog Timers Revision History
1.19. UART Controller Revision History
1.20. GPIO Revision History
1.21. I/O Pin Multiplexing Revision History
1.22. System Manager Revision History
1.23. Clock Manager Revision History
1.24. Reset Manager Revision History
1.25. Power Management Revision History
1.26. Bridges Revision History
1.27. HPS Mailbox Revision History
1.28. MPFE and MPFE-lite Revision History
1.29. EMAC GMII through FPGA Fabric Revision History
1.30. System Interconnect and Firewalls Revision History
1.31. ECC Controller Revision History
1.32. CoreSight* Debug and Trace Revision History
1.33. HPS Register Map Revision History
1.34. Booting and Configuration Revision History
1.35. HPS Use of SDM QSPI Controller Revision History
1.36. Security Revision History
1.37. Operational Status of the HPS to the FPGA Logic Revision History
2.3.1. HPS Block Diagram
2.3.2. MPU Features
2.3.3. Application Processor Subsystem
2.3.4. Peripheral Subsystem
2.3.5. System Manager Features
2.3.6. Clock Manager Features
2.3.7. Reset Manager Features
2.3.8. Bridges Features
2.3.9. System Interconnect and Firewalls Features
2.3.10. ECC Controller Features
2.3.11. CoreSight Debug and Trace Features
2.3.4.1. EMAC Features
2.3.4.2. DMA Controller Features
2.3.4.3. NAND Flash Controller Features
2.3.4.4. Combo DLL PHY Features
2.3.4.5. USB 3.1 Gen1 Controller Features
2.3.4.6. USB 2.0 OTG Controller Features
2.3.4.7. I3C Controller Features
2.3.4.8. I2C Controller Features
2.3.4.9. SPI Controller Features
2.3.4.10. Timers Features
2.3.4.11. Watchdog Timers Features
2.3.4.12. UART Controller Features
2.3.4.13. GPIO Features
2.3.4.14. I/O Pin Multiplexing Features
3.1. MPU Differences Among Intel SoC Device Families
3.2. MPU Use Cases
3.3. MPU Features
3.4. MPU System Integration
3.5. MPU Arm* Cortex* -A76 Core
3.6. MPU Arm* Cortex* -A55 Core
3.7. MPU Arm* DynamIQ Shared Unit
3.8. MPU Clock Domains
3.9. MPU Reset Domains
3.10. MPU Power Domains
3.11. MPU Address Map and Register Definitions
3.5.3.1. Cortex* -A76 Core Configuration
3.5.3.2. Exception Levels
3.5.3.3. Virtualization
3.5.3.4. Memory Management Unit
3.5.3.5. Level 1 Memory System
3.5.3.6. Level 2 Memory System
3.5.3.7. Generic Interrupt Controller CPU Interface
3.5.3.8. Advanced Single Instruction Multiple Data and Floating Point Support
3.5.3.9. Cryptographic Extensions
3.5.3.10. Generic Timer
3.5.3.11. Cache Protection
3.5.3.12. Debug
3.6.3.1. Cortex* -A55 Core Configuration
3.6.3.2. Exception Levels
3.6.3.3. Virtualization
3.6.3.4. Memory Management Unit
3.6.3.5. Level 1 Memory System
3.6.3.6. Level 2 Memory System
3.6.3.7. Generic Interrupt Controller CPU Interface
3.6.3.8. Data Processing Unit
3.6.3.9. Generic Timer
3.6.3.10. Cache Protection
3.6.3.11. Debug
4.1.5.1. Block Diagram
4.1.5.2. Ports
4.1.5.3. Cache Coherency Protocol
4.1.5.4. Addressing and Memory Regions
4.1.5.5. Connectivity
4.1.5.6. Snoop Filters
4.1.5.7. System Memory Cache
4.1.5.8. Credits and Resources
4.1.5.9. Quality of Service
4.1.5.10. Storage Protection
4.1.5.11. Exclusive Monitors
4.1.5.12. Firewall and Security
4.1.5.13. Interrupts
4.1.5.14. Clocks
4.1.5.15. Resets
4.1.5.16. Power Management
4.1.5.17. Shutdown of Interfaces
4.1.5.18. Error Handling
4.1.5.19. CCU Restrictions
4.1.5.2.1. DSU CHI-B Initiator Port
4.1.5.2.2. F2H ACE-Lite Initiator Port
4.1.5.2.3. GIC_M ACE-lite Initiator Port
4.1.5.2.4. TCU Ace-lite+DVM Initiator Port
4.1.5.2.5. CCU_IOM ACE-Lite Initiator Port
4.1.5.2.6. CCU_DMI0, CCU_DMI1 1AXI4 Target Ports
4.1.5.2.7. CCU_IOS AXI Target Port
4.1.5.2.8. MPFE CSR AXI Target Port
4.1.5.2.9. GIC AXI Target Port
4.1.5.2.10. OCRAM AXI Target Port
4.3.1. SMMU Differences Among Intel SoC Device Families
4.3.2. SMMU Use Cases
4.3.3. SMMU Features
4.3.4. SMMU System Integration
4.3.5. SMMU Signal Description
4.3.6. SMMU Functional Description
4.3.7. SMMU Programming Model
4.3.8. SMMU Address Map and Register Definitions
4.3.9. SMMU Design Guidelines and Examples
4.3.7.1. Initializing the SMMU
4.3.7.2. Assigning Stream IDs
4.3.7.3. Allocating the Command Queue
4.3.7.4. Allocating the Event Queue
4.3.7.5. Configuring the Stream Table
4.3.7.6. Initializing the Command Queue
4.3.7.7. Initializing the Event Queue
4.3.7.8. Invalidate TLBs and Configuration caches
4.3.7.9. Create Context Descriptor
4.3.7.10. Creating Stream Table Entry
4.3.7.11. Enabling the SMMU
5.1. Ethernet Media Access Controller
5.2. DMA Controller
5.3. NAND Flash Controller
5.4. SD/eMMC Host Controller
5.5. Combo DLL PHY
5.6. USB 3.1 Gen1 Controller
5.7. USB 2.0 OTG Controller
5.8. I3C Controller
5.9. I2C Controller
5.10. SPI Controller
5.11. Timers
5.12. Watchdog Timers
5.13. UART Controller
5.14. General-Purpose I/O Interface (GPIO)
5.15. Hard Processor System I/O Pin Multiplexing
5.1.1. EMAC Differences Among Intel SoC Device Families
5.1.2. EMAC Use Cases
5.1.3. EMAC Features
5.1.4. EMAC System Integration
5.1.5. EMAC Signal Description and Interfaces
5.1.6. EMAC Functional Description
5.1.7. EMAC Programming Model
5.1.8. EMAC Address Map and Register Definitions
5.1.9. EMAC Design Guidelines and Examples
5.1.6.1. External Memory
5.1.6.2. DMA Controller
5.1.6.3. Descriptor
5.1.6.4. Checksum Offload Engine (COE)
5.1.6.5. TCP Segmentation Offload
5.1.6.6. Packet Filtering
5.1.6.7. Management Counter
5.1.6.8. Flow Control
5.1.6.9. IEEE 1588-2008 Advanced Timestamp
5.1.6.10. TSN Features
5.1.6.11. SMTG Hub Time of Day Synchronization
5.1.6.12. Clocks
5.1.6.13. Resets
5.1.6.14. Interrupts
5.1.6.2.1. Application Bus Burst Access
5.1.6.2.2. Application Data Buffer Alignment
5.1.6.2.3. Buffer Size Calculations
5.1.6.2.4. DMA Descriptor Fetch Operation
5.1.6.2.5. DMA TX Data Transfer Operation
5.1.6.2.6. DMA RX Data Transfer Operation
5.1.6.2.7. DMA Descriptor Write-Back Operation
5.1.6.2.8. DMA Start/Stop Operation
5.1.6.2.9. Memory Cache Size Requirements
5.1.6.2.10. Memory Cache Access Arbitration
5.1.6.2.11. DMA Error Handling
5.1.7.1. System Level EMAC configurable Registers
5.1.7.2. EMAC HPS Interface Initialization
5.1.7.3. EMAC FPGA Interface Initialization
5.1.7.4. DMA Initialization
5.1.7.5. EMAC Initialization and Configuration
5.1.7.6. Performing Normal Receive and Transmit Operation
5.1.7.7. Stopping and Starting Transmission
5.1.7.8. Reconfiguring the DMA Registers
5.1.7.9. Switching to a New Descriptor List in the Receive DMA
5.1.7.10. Handling Bus Errors and Recovery
5.1.7.11. Setting up TCP Segmentation Offload
5.1.7.12. Setting up VLAN Filtering on Receive
5.1.7.13. Setting up Extended VLAN Filtering
5.1.7.14. Setting up the L3-L4 Filtering
5.1.7.15. Programming the SMTG Hub
5.1.7.16. Setting up the IEEE 1588 PTP Timestamping
5.1.7.17. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
5.1.7.18. Programming the GCL and GCL Linked Registers
5.1.7.19. Programming Guidelines for EST
5.1.7.20. Enabling the Frame Preemption Function
5.1.7.21. Setting up the Time-Based Scheduling Function
5.3.1. NAND Flash Controller Differences Among Intel SoC Device Families
5.3.2. NAND Flash Controller Use Cases
5.3.3. NAND Flash Controller Features
5.3.4. NAND Flash Controller System Integration
5.3.5. NAND Flash Controller Signal Description
5.3.6. NAND Flash Controller Functional Description
5.3.7. NAND Flash Controller Programming Model
5.3.8. NAND Flash Controller Address Map and Register Definitions
5.3.6.1. Block Diagram
5.3.6.2. Initialization Protocol (Device Discovery)
5.3.6.3. NAND Flash Addressing and Data Layout
5.3.6.4. Command Engine Functionality
5.3.6.5. ECC Engine Functionality
5.3.6.6. Control Data Mechanism
5.3.6.7. Remapping Mechanism
5.3.6.8. Write Protection Mechanism
5.3.6.9. Error and Special Scenarios Handling
5.3.6.10. Controller Fixed Parameters and Clock Frequencies Supported
5.3.7.1. NAND Controller Registers Programming Model
5.3.7.2. Status Polling Configuration
5.3.7.3. Device Layout Configuration
5.3.7.4. Configure Multiplane and Cache Operations
5.3.7.5. ECC Enabling
5.3.7.6. Interrupts Configuration
5.3.7.7. Configuring Timing Registers
5.3.7.8. Switch from SDR to DDR Operation Mode
5.3.7.9. Switch from DDR to SDR Operation Mode
5.3.7.10. Slave DMA Programming
5.3.7.11. Data Pre-Fetching Mechanism
5.3.7.12. Data Integrity Mechanism
5.3.7.13. Enabling pSLC Mode for the TLC Devices
5.4.1. SD/eMMC Differences Among Intel SoC Device Families
5.4.2. SD/eMMC Use Cases
5.4.3. SD/eMMC Features
5.4.4. SD/eMMC System Integration
5.4.5. SD/eMMC Signal Description
5.4.6. SD/eMMC Functional Description
5.4.7. SD/eMMC Programming Model
5.4.8. SD/eMMC Address Map and Register Definitions
5.4.9. SD/eMMC Design Guidelines and Examples
5.4.6.1.1. Bus Interface Unit
5.4.6.1.2. Reset Control Module
5.4.6.1.3. Synchronization Module
5.4.6.1.4. Response Module
5.4.6.1.5. FIFO Interface Unit
5.4.6.1.6. Card Interface Unit
5.4.6.1.7. System Requester Interface
5.4.6.1.8. System Manager Interface
5.4.6.1.9. Host Settings Interface
5.4.6.1.10. Command Queue Settings
5.5.1. Combo DLL PHY Differences Among Intel SoC Device Families
5.5.2. Combo DLL PHY Use Cases
5.5.3. Combo DLL PHY Features
5.5.4. Combo DLL PHY System Integration
5.5.5. Combo DLL PHY Signal Description
5.5.6. Combo DLL PHY Functional Description
5.5.7. Combo DLL PHY Programming Model
5.5.8. Combo DLL PHY Address Map and Register Definitions
5.6.1. USB 3.1 Gen1 Controller Differences Among Intel SoC Device Families
5.6.2. USB 3.1 Gen1 Controller Use Cases
5.6.3. USB 3.1 Gen1 Controller Features
5.6.4. USB 3.1 Gen1 Controller System Integration
5.6.5. USB 3.1 Gen1 Controller Functional Description
5.6.6. USB 3.1 Gen1 Controller Programming Model
5.6.7. USB 3.1 Gen1 Controller Address Map and Register Definitions
5.6.8. USB 3.1 Gen1 Controller Design Guidelines and Examples
5.6.5.1. Manager Interface
5.6.5.2. AHB Subordinate Interface
5.6.5.3. Application interface Unit
5.6.5.4. Bus Management Unit
5.6.5.5. Packet FIFO Controller
5.6.5.6. RAM
5.6.5.7. MAC
5.6.5.8. DMA
5.6.5.9. Loopback
5.6.5.10. PHY Interfaces
5.6.5.11. USB 3.1 Gen1 Controller Clocks
5.6.5.12. USB 3.1 Gen1 Controller Resets
5.6.6.2.1. Device Power-on or Soft Reset
5.6.6.2.2. Initialization on USB Reset
5.6.6.2.3. Initialization on Connect Done
5.6.6.2.4. Initialization on SetAddress Request
5.6.6.2.5. Initialization on SetConfiguration or SetInterface Request
5.6.6.2.6. Agilex 5 Programming Model
5.6.6.2.7. Controller as Host
5.7.1. USB 2.0 OTG Controller Differences Among Intel SoC Device Families
5.7.2. USB 2.0 OTG Controller Use Cases
5.7.3. USB 2.0 OTG Controller Features
5.7.4. USB 2.0 OTG Controller System Integration
5.7.5. USB 2.0 OTG Controller Functional Description
5.7.6. USB 2.0 OTG Controller Programming Model
5.7.7. USB 2.0 OTG Controller Address Map and Register Definitions
5.8.1. I3C Controller Differences Among Intel SoC Device Families
5.8.2. I3C Controller Use Cases
5.8.3. I3C Controller Features
5.8.4. I3C Controller System Integration
5.8.5. I3C Controller Signal Description
5.8.6. I3C Controller Functional Description
5.8.7. I3C Controller Programming Model
5.8.8. I3C Controller Address Map and Register Definitions
5.8.9. I3C Controller Design Guidelines and Examples
5.8.6.5.1. Dynamic Address Assignment (DAA)
5.8.6.5.2. In-Band Interrupt (IBI) Detection and Handling
5.8.6.5.3. I3C Slave Interrupt Request (SIR)
5.8.6.5.4. Disabling I3C Master
5.8.6.5.5. Aborting Transfers of I3C Master
5.8.6.5.6. I3C Master Request (MR)
5.8.6.5.7. Master Command Data Structures
5.8.6.5.8. Response Data Structure
5.8.6.5.9. Operation Modes of I3C Controller
5.8.6.5.10. SCL Generation and Timings Based on Bus Configuration
5.8.6.5.11. Derivation of I3C/I2C Timing Parameters from Timing Registers
5.8.6.5.12. Error Detection
5.8.6.5.13. Defining Byte Support
5.8.6.5.14. Broadcast CCCs in I2C Speed
5.8.6.5.15. BUS RESET Generation DMA Controller Interface
5.8.6.5.9.1. Single Data Rate (SDR) Transfers in Master Mode
5.8.6.5.9.2. Broadcast CCC Write Transfers
5.8.6.5.9.3. Directed Write and Read Transfers
5.8.6.5.9.4. Directed CCC Transfer Targeted to Multiple Slaves
5.8.6.5.9.5. I3C Private Write or Read Transfers
5.8.6.5.9.6. I2C Private Write or Read Transfers
5.8.6.5.9.7. Implication of TX-FIFO Empty and RX-FIFO Full Conditions
5.8.6.5.9.8. Implication of TOC and ROC Bit Settings for SDR Transfers
5.8.6.6.1. Description of the Slave Role in I3C
5.8.6.6.2. I3C versus I2C Role Selection
5.8.6.6.3. Slave Role Related Registers
5.8.6.6.4. Handling Address Assignment
5.8.6.6.5. CCC Transfers with I3C Slave
5.8.6.6.6. Private Data Transfers
5.8.6.6.7. Handling Private Transmit (Master Read) Transfers
5.8.6.6.8. Slave Interrupt Request Generation
5.8.6.6.9. Master Request Generation
5.8.6.6.10. Disabling I3C Slave
5.8.6.6.11. Data Structure in I3C Slave
5.8.7.6.1. Private Receive (Master Write) Transfers in Slave Mode
5.8.7.6.2. Private Transmit (Master Read) Transfers in Slave Mode
5.8.7.6.3. Programming Flow for Generating Slave Interrupt Request
5.8.7.6.4. Programming Flow for Generating Master Request
5.8.7.6.5. Programming Flow to Prepare the Controller to Switch to Master Mode
5.8.7.6.6. Command Pipeline and Aggregation of Response Queue Threshold Interrupt
5.8.7.6.7. Error Recovery Flow
5.8.7.6.8. CCC Updated Interrupt Flow
5.8.7.6.9. Flow for Disable and TX/RX/CMD/Response Queue Reset
5.9.1. I2C Controller Differences Among Intel SoC Device Families
5.9.2. I2C Controller Use Cases
5.9.3. I2C Controller Features
5.9.4. I2C Controller System Integration
5.9.5. I2C Controller Signal Description
5.9.6. I2C Controller Functional Description
5.9.7. I2C Controller Programming Model
5.9.8. I2C Controller Address Map and Register Definitions
5.9.9. I2C Controller Design Guidelines and Examples
5.10.1. SPI Controller Differences Among Intel SoC Device Families
5.10.2. SPI Controller Use Cases
5.10.3. SPI Controller Features
5.10.4. SPI Controller System Integration
5.10.5. SPI Controller Signal Description
5.10.6. SPI Controller Functional Description
5.10.7. SPI Controller Programming Model
5.10.8. SPI Controller Address Map and Register Definitions
5.10.6.1. Protocol Details and Standards Compliance
5.10.6.2. Overview
5.10.6.3. Serial Bit-Rate Clocks
5.10.6.4. Transmit and Receive FIFO Buffers
5.10.6.5. SPI Interrupts
5.10.6.6. Transfer Modes
5.10.6.7. SPI Master
5.10.6.8. SPI Slave
5.10.6.9. Partner Connection Interfaces
5.10.6.10. DMA Controller Interface
5.10.6.11. Slave Interface
5.10.6.12. Clocks and Resets
5.12.1. Watchdog Timers Differences Among Intel SoC Device Families
5.12.2. Watchdog Timers Use Cases
5.12.3. Watchdog Timers Features
5.12.4. Watchdog Timers System Integration
5.12.5. Watchdog Timers Functional Description
5.12.6. Watchdog Timers Programming Model
5.12.7. Watchdog Timers Address Map and Register Definitions
5.12.6.1. Setting the Timeout Period Values
5.12.6.2. Selecting the Output Response Mode
5.12.6.3. Enabling and Initially Starting a Watchdog Timers
5.12.6.4. Reloading a Watchdog Counter
5.12.6.5. Pausing a Watchdog Timers
5.12.6.6. Disabling and Stopping a Watchdog Timers
5.12.6.7. Watchdog Timers State Machine
5.13.1. UART Controller Differences Among Intel SoC Device Families
5.13.2. UART Controller Use Cases
5.13.3. UART Controller Features
5.13.4. UART Controller System Integration
5.13.5. UART Controller Signal Description
5.13.6. UART Controller Functional Description
5.13.7. UART Controller Address Map and Register Definitions
5.13.8. UART Controller Design Guidelines and Example
5.15.1. I/O Pin Multiplexing Differences Among Intel SoC Device Families
5.15.2. I/O Pin Multiplexing Use Cases
5.15.3. I/O Pin Multiplexing Features
5.15.4. I/O Pin Multiplexing System Integration
5.15.5. I/O Pin Multiplexing Functional Description
5.15.6. I/O Pin Multiplexing Address Map and Register Definitions
5.15.7. I/O Pin Multiplexing Design Guidelines and Examples
6.4.1.1. DMA Controller
6.4.1.2. NAND Flash Controller
6.4.1.3. EMAC
6.4.1.4. USB 2.0 OTG Controller
6.4.1.5. USB 3.1 Controller
6.4.1.6. NOC Registers
6.4.1.7. Boot Scratch Space
6.4.1.8. I3C Controller
6.4.1.9. SD/eMMC Controller
6.4.1.10. GPIO Interconnect Between the HPS and FPGA
6.4.1.11. Watchdog Timer
7.1. Clock Manager Differences Among Intel SoC Device Families
7.2. Clock Manager Use Cases
7.3. Clock Manager Features
7.4. Clock Manager System Integration
7.5. Clock Manager Signal Description
7.6. Clock Manager Functional Description
7.7. Clock Manager Programming Model
7.8. Clock Manager Address Map and Register Definitions
7.9. Clock Manager Design Guidelines and Examples
7.2.1. A76 Core Power and Performance Trade-off
7.2.2. A55 Core Power and Performance Trade-off
7.2.3. DSU Power and Performance Trade-off
7.2.4. Peripheral Clock Generation
7.2.5. Peripheral Power Optimization
7.2.6. Clock Tree Clock Sources
7.2.7. Boot Clock
7.2.8. Power-on-reset
7.2.9. Boot Mode
7.2.10. Disable Clocks Before Reset Assertion
7.2.11. PLL Configuration using JTAG
7.6.1. PLL Wrapper
7.6.2. MPU/DSU and APS/CCU Clock Groups
7.6.3. PSS Clock Group
7.6.4. MPFE Clock Group
7.6.5. EMAC and XGMAC Clock Group
7.6.6. USB31 Clock Group
7.6.7. SD/eMMC, NAND, and SoftPHY/ComboPHY
7.6.8. H2F User Clock Group
7.6.9. F2H User Clock Group
7.6.10. GPIO Debounce Clock Group
7.6.11. CoreSight Clocks
7.6.12. PSI Clock Group (to the SDM)
7.7.1. Example Configuration of Registers for Default Operation (640 MHz CPU)
7.7.2. Example Configuration of Registers for Power Optimized (1000 MHz CPU)
7.7.3. Example Configuration of Registers for Performance Optimized (1800 MHz CPU)
7.7.4. Example Configuration of Registers for Power Optimized (1200 MHz CPU)
7.7.5. Summary Table of Registers Used to Program Clocks
8.1. Reset Manager Differences Among Intel SoC Device Families
8.2. Reset Manager Use Cases
8.3. Reset Manager Features
8.4. Reset Manager System Integration
8.5. Reset Manager Signal Description
8.6. Reset Manager Functional Description
8.7. Reset Manager Programming Model
8.8. Reset Manager Address Map and Register Definitions
11.1. Bridges Differences Among Intel SoC Device Families
11.2. Bridges Use Cases
11.3. Bridges Features
11.4. Bridges System Integration
11.5. Bridges Functional Description
11.6. Bridges Clocks and Resets
11.7. Bridges Address Map and Register Definitions
11.8. Bridges Design Guidelines and Examples
12.2.1. MPFE and MPFE-lite Terminology
12.2.2. MPFE and MPFE-lite Differences Among Intel SoC Families
12.2.3. MPFE and MPFE-lite Use Cases
12.2.4. MPFE and MPFE-lite Features
12.2.5. MPFE and MPFE-lite System Integration
12.2.6. MPFE and MPFE-lite Functional Description
12.2.7. MPFE and MPFE-lite Address Map and Register Definitions
12.2.3.1. Fabric Bypass
12.2.3.2. One 16-bit SDRAM channel
12.2.3.3. One 32-bit SDRAM channel
12.2.3.4. Two 16-bit SDRAM channels utilizing a single IOBank
12.2.3.5. Two 16-bit or two 32-bit SDRAM channels utilizing two IOBank
12.2.3.6. Four 16-bit SDRAM channels utilizing two IOBank
12.2.3.7. Supports up to 512GB of memory
12.2.3.8. Supports sideband ECC on DDR4/5
12.2.3.9. Supports inband ECC on LPDDR4/5
12.2.6.1. Block Diagram
12.2.6.2. Interfaces
12.2.6.3. AxUSER Bit Connectivity
12.2.6.4. Fabric Bypass
12.2.6.5. FPGA-to-SDRAM bridge
12.2.6.6. FPGA-to-HPS bridge
12.2.6.7. MPFE NoC
12.2.6.8. MPFE-lite / MPFE-lite NoC
12.2.6.9. Address Gap Glue Logic
12.2.6.10. Resets Circuitry
12.2.6.11. Clocks Circuitry
12.2.6.12. Preserving SDRAM contents
13.1. System Interconnect and Firewalls Differences Among Intel SoC Device Families
13.2. System Interconnect and Firewalls Features
13.3. System Interconnect and Firewalls System Integration
13.4. System Interconnect and Firewalls Functional Description
13.5. System Interconnect and Firewalls Address Map and Register Definitions
13.4.4.1. Priority Levels
13.4.4.2. Urgency and Pressure Signals
13.4.4.3. Passing QOS across NoCs
13.4.4.4. QoS Generators
13.4.4.5. Configuring the Quality of Service Logic
13.4.4.6. Programming QoS Limiter Mode
13.4.4.7. Programming QoS Regulator Mode
13.4.4.8. Programming QoS Fixed Mode
13.4.4.9. Bandwidth and Saturation
13.4.4.10. QoS Programming Examples
14.6.1. ECC Structure
14.6.2. Memory Data Initialization
14.6.3. Indirect Memory Access
14.6.4. Error Checking and Correction Algorithm
14.6.5. Error Logging
14.6.6. ECC Controller Interrupts
14.6.7. ECC Controller Initialization and Configuration
14.6.8. ECC Controller Clocks
14.6.9. ECC Controller Reset
15.1. CoreSight* Debug and Trace Differences Among Intel SoC Device Families
15.2. CoreSight Debug and Trace Use Cases
15.3. CoreSight Debug and Trace Features
15.4. CoreSight* Debug and Trace System Integration
15.5. CoreSight Debug and Trace Functional Description
15.6. CoreSight Debug and Trace Programming Model
15.7. CoreSight* Debug and Trace Address Map and Register Definitions
15.5.2.1. Embedded Trace Macrocell (ETM)
15.5.2.2. System Trace Macrocell (STM)
15.5.2.3. PSS NOC and MPFE NOC
15.5.2.4. AMBA* Trace Bus (ATB)
15.5.2.5. Trace Port Interface Unit (TPIU)
15.5.2.6. Embedded Trace FIFO (ETF)
15.5.2.7. Embedded Trace Router (ETR)
15.5.2.8. ATB IDs
15.5.2.9. NOC Trace Observability
15.5.2.10. STM HWEVENT Connectivity
A.2.1. HPS Use of SDM QSPI Controller Differences Among Intel SoC Device Families
A.2.2. HPS Use of SDM QSPI Controller Use Cases
A.2.3. HPS Use of SDM QSPI Controller Features
A.2.4. HPS Use of SDM QSPI Controller System Integration
A.2.5. HPS Use of SDM QSPI Controller Signal Description
A.2.6. HPS Use of SDM QSPI Controller Functional Description
A.2.7. HPS Use of SDM QSPI Controller Programming Model
A.2.8. HPS Use of SDM QSPI Controller Address Map and Register Definitions
A.2.9. HPS Use of SDM QSPI Controller Design Guidelines and Examples
A.2.6.1. Data Target Interface
A.2.6.2. Register Target Interface
A.2.6.3. Local Memory Buffer
A.2.6.4. Arbitration between Direct/Indirect Access Controller and STIG
A.2.6.5. Configuring the Flash Device
A.2.6.6. Write Protection
A.2.6.7. Data Target Sequential Access Detection
A.2.6.8. Clocks
A.2.6.9. Resets
A.2.6.10. Interrupts
Visible to Intel only — GUID: psd1672444548494
Ixiasoft
2.3.2.2. Arm* Cortex* -A55 Core Features
The Cortex* -A55 core includes the following features:
Core features:
- Full implementation of the Arm* v8.2-A A64, A32, and T32 instruction sets
- Both the AArch32 and AArch64 execution states at all exception levels (EL0 to EL3)
- In-order pipeline with direct and indirect branch prediction
- Separate L1 data and instruction side memory systems with MMU
- Support for Arm* TrustZone technology
- Data engine that implements the advanced SIMD and floating-point architecture support
- Cryptographic extension
- Generic interrupt controller (GIC) CPU interface to connect to an external distributor
- Generic timers interface supporting 64-bit count input from an external system counter
Cache features:
- Separate L1 data and instruction caches per core
- Private, unified data and instruction L2 cache per core
- L1 and L2 cache protection in the form of error checking and correction (ECC) or parity on all RAM instances
Debug features:
- Reliability, availability, and serviceability (RAS) extension
- Armv8.2-A debug logic
- Performance monitoring unit (PMU)
- Embedded trace macrocell (ETM) that supports instruction trace only