Visible to Intel only — GUID: cpj1676420076243
Ixiasoft
Visible to Intel only — GUID: cpj1676420076243
Ixiasoft
11.6.3. Lightweight HPS-to-FPGA Bridge Clocks and Resets
The initiator interface into the FPGA fabric operates in the lwhps2fpga_axi_clock clock domain. The clock is provided by custom logic in the FPGA fabric. The responder interface of the bridge in the HPS logic operates in the l3_main_clk clock domain. The bridge provides clock crossing logic that allows the logic in the FPGA to operate in any clock domain, asynchronous from the HPS. The LWH2F bridge has one reset signal, lwhps2fpga_axi_reset. The reset manager asserts this signal to the LWH2F bridge on a cold or warm reset.