Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.6.5.12.1. Reset Requirements

All internal resets are active simultaneously for some period. The reset module of the controller takes care of this by asynchronously propagating vcc_reset_n to all the internal resets in the design.

For the external USB 3.1 and USB 2.0 PHY. the controller provides pipe_reset_n and usb2phy_reset signals to achieve these requirement.

The controller drives the pipe_reset_n and usb2phy_reset outputs active as long as vcc_reset_n and ctrlr_pipe_reset_n are active, and phy_rst_stgg_pulse is triggered.