Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.1.6.8.1. Transmit Flow Control

The transmit flow control involves transmitting pause packets in full-duplex mode and back pressure in half-duplex mode, to control the flow of packets from the remote end. The transmit flow control is enabled independently for each priority, using priority flow control (PFC) packets in PFC mode (PFCE bit set to 1 in the MAC_Rx_Flow_Ctrl register), when the TFE bit is set in the MAC_Q(#i)_Tx_Flow_Ctrl register. In non-PFC mode, only PAUSE packets are transmitted as per the MAC_Q0_Tx_Flow_Ctrl register.

Flow Control Trigger

The application can request the MAC to send a pause packet by using either of the following methods:
  • Software Trigger: In this method, the application sets the FCB bit in the corresponding MAC_Q(#i)_Tx_Flow_Ctrl register.
  • Hardware Trigger: In this method, the application triggers the flow control by asserting the mti_flowctrl_i signal. The mti_flowctrl_i signal is an internal input signal to the MAC.
The flow control is triggered based on the following:
  • RX Queue Threshold: The flow control operation of the MAC is enabled when the EHFC bit of corresponding MTL_RxQ(#i)_Operation_Mode register is set. The flow control signal to the MAC is asserted when the fill level of the RX queue crosses the threshold configured in RFA field of MTL_RxQ(#i)_Flow_Control register. This flow control signal is de-asserted when the fill-level of the queue falls below the threshold configured in the RFD field.

The hardware flow control generated based on the RX queue threshold crossing condition is applicable only when the RX queue size is 4,096 bytes or more.

Flow Control in Half-Duplex Mode

In half-duplex mode, the MAC uses the deferral mechanism for the flow control (back pressure). When the application requests to stop receiving packets, the MAC sends a JAM pattern of 32 bytes when it senses a packet reception, provided the transmit flow control is enabled. This results in a collision and the remote station backs off. If the application requests a packet to be transmitted, it is scheduled and transmitted even when the back pressure is activated. If the back pressure is active for a long time (more than 16 consecutive collision events occur), the remote stations abort the transmission because of excessive collisions. Flow control is similar for all queues.

Flow Control in Full Duplex Mode

The EMAC uses one of the following packet types for flow control:
  • IEEE 802.3x-2018 pause packets
  • Priority flow control (PFC) packets

The PFC packets are used only when the enable data priority flow control option is selected. The PFCE bit of the MAC_Rx_Flow_Ctrl register determines whether PFC packets or pause control packets are used for flow control. If the PFCE bit is set, the MAC sends the PFC packets. Each MAC_Q(#i)_Tx_Flow_Ctrl register controls the PFC packet generation and content for the corresponding RxQ(#i) flow control trigger and priorities of packets mapped to that queue. Similarly, the sbd_flow_ctrl_i is a multi-bit signal, each bit is associated with the corresponding MAC_Q(#i)_Tx_Flow_Ctrl register.

When PFCE bit is reset, MAC can send only a pause packet as per the programming of the MAC_Q0_Tx_Flow_Ctrl register. All the other MAC_Q[1:7]_Tx_Flow_Ctrl registers are ignored. In this mode, assertion of any bit in the multi-bit sbd_flow_ctrl_i (if present) triggers the flow control while de-assertion of all bits is taken as the de-activation of pause flow control.
Table 153.  Pause Packet Fields
Octets Field Pause Packet PFC Packet
0 - 5 DA Special Multicast address = 0180-c200-0001  
6 - 11 SA MAC_Adddress0 register  
12 - 13 Type Control type = 0x8808  
14 - 15 Opcode 0x0001 0x0101
16 - 17 PT/PEV

PT field of MAC_Q0_Tx_Flow_Ctrl

register

Priority Enable Vector indicating

which of the following PT# fields

are valid

18 - 19 PT0 Reserved

PT field of MAC_Q0_Tx_Flow_Ctrl

register

20 - 21 PT1 Reserved

PT field of MAC_Q1_Tx_Flow_Ctrl

register

... ... Reserved  
32 - 33 PT7 Reserved

PT field of MAC_Q7_Tx_Flow_Ctrl

register

34 - 59 ... Reserved  
60 - 63 FCS CRC CRC

Pause Packet Control

When the FCB bit is set, the MAC generates and transmits a single pause packet. If the FCB bit is set again after the pause packet transmission is complete, the MAC sends another pause packet irrespective of whether the pause time is complete or not. To extend the pause or terminate the pause prior to the time specified in the previously transmitted pause packet, the application must program the pause time register with appropriate value and then set the FCB bit again.

Similarly, when the mti_flowctrl_i signal (any bit in a multi-bit bus) is asserted, the MAC generates and transmits a single pause packet. If the mti_flowctrl_i signal remains asserted at a configurable number of slot times before the pause time runs out, the MAC transmits a second pause packet. This process is repeated as long as the mti_flowctrl_i signal remains active. If the mti_flowctrl_i signal goes inactive (all bits in a multi-bit bus) prior to the sampling time, the MAC transmits a pause packet with zero pause time (if the DZPQ bit in MAC_Q(#i)_Tx_Flow_Ctrl register is set to 0) to indicate to the remote end that the receive buffer is ready to receive new data packets.

For PFC packets, you can specify the priority, pause time, and other controls for a queue in the MAC_Q(#i)_Tx_Flow_Ctrl register. The MAC supports independent flow control for each RX queue and the priorities of packets in that queue is taken from the corresponding PSRQ fields of the MAC_RxQ_Ctrl2/3 registers. There is one trigger input for each RX queue. When activated, the priority bits set in that RX queue PSRQ(#i) field is also set in the PEV fields, and the PT of the corresponding MAC_Q(#i)_Tx_Flow_Ctrl is inserted in the PT(#i) field of the PFC packet. If multiple priorities are programmed in the same RX queue, multiple priorities are set for the PFC packet with the same pause time values. For example, when mti_flow_ctrl_i[4] is high and PSRQ4 = 0x05 (priority 0 and priority 2), the PEV field is also set to 0x05 and the PT of MAC_Q4_Tx_Flow_Ctrl register is inserted in PT0 and PT2 fields of the PFC packet. When the mti_flow_ctrl_i[4] signal becomes low and the DZPQ of MAC_Q4_Tx_Flow_Ctrl register is set, a PFC packet with PEV = 0x05 and PT0 and PT2 = 0 (Zero quanta PFC) is transmitted.

When multiple triggers come simultaneously, the MAC sends one consolidated PFC packet. This PFC packet has the PEV set to the combined (ORed) values of the corresponding PSRQ[i] fields and the respective PT[i] fields are taken from the appropriate MAC_Q(#i)_Tx_Flow_Ctrl registers. This reduces the PFC traffic on the transmitter and improves data throughput.

TX Path Flow Control Registers

The flow control in the TX path for queue0 is based on the setting of the following bits:
  • EHFC bit of the MTL_RxQ0_Operation_Mode register
  • TFE and FCB bits of the MAC_Q0_Tx_Flow_Ctrl register
  • HD (Half-duplex mode) bit of MAC_Extended_Configuration register
Table 154.  Flow Control in TX Path
EHFC TFE HD Description
x 0 x The MAC transmitter does not perform the flow control or back pressure operation.
0 1 1 The MAC transmitter performs back pressure when bit 0 of MAC_Q0_Tx_Flow_Ctrl register is set or the sideband signal sbd_flowctrl_i is 1.
1 1 1 The MAC transmitter performs back pressure when bit 0 of MAC_Q0_Tx_Flow_Ctrl register is set or the sideband signal sbd_flowctrl_i is 1. In addition, the MAC TX performs back pressure when RX queue level crosses the threshold set by RFA field of MTL_RxQ#_Flow_Control register.
0 1 0 The MAC transmitter sends the pause packet when bit 0 of the MAC_Q0_Tx_Flow_Ctrl register is set or the sideband signal sbd_flowctrl_i is 1.
1 1 0

The MAC transmitter sends the pause packet when bit 0 of the MAC_Q0_Tx_Flow_Ctrl register is set or the sideband signal sbd_flowctrl_i is 1.

In addition, the MAC Tx sends a Pause packet when Rx Queue level crosses the threshold set by Bits[10:8] of MTL_RxQ0_Operation_Mode register.