Visible to Intel only — GUID: kil1678722643339
Ixiasoft
Visible to Intel only — GUID: kil1678722643339
Ixiasoft
12.2.6.2. Interfaces
The MPFE has interfaces that allow it to communicate to the Fabric core logic, the SDRAM, and the HPS. An overview of these interfaces is available in the table below. Further details are provided in the sections following the table.
Group |
Interface Name |
Initiator |
Protocol |
Width |
Comment |
---|---|---|---|---|---|
Fabric |
FPGA-to-HPS |
Fabric core logic |
ACE lite |
256-bit |
The IO coherent port from the Fabric into the CCU/NCORE. Can access HPS peripherals, OCRAM, and DRAM. Supports atomic operations in the interconnect. |
FPGA-to-SDRAM |
Fabric core logic |
AXI4 |
256/128/64-bit |
Non-coherent fabric access to SDRAM. |
|
HPS |
CCU_DMI0 |
CCU/NCORE |
AXI4 |
256-bit |
CCU/NCore target NIU for SDRAM bound traffic |
CCU_DMI1 |
CCU/NCORE |
AXI4 |
256-bit |
CCU/NCore target NIU for SDRAM bound traffic. Only used when traffic is interleaved between Ports. |
|
MPFE_CSR |
CCU/NCORE |
AXI4 |
64-bit |
HPS access to the MPFE NoC, IOBank0 and IOBank1 CSRs. |
|
NOC_OBS |
MPFE |
ATB |
~50 bits |
NOC observation signals (debug) from the MPFE NOC to the CoreSight* System. |
|
MPFE_TBU |
TCU |
AXIS |
72-bits (TBU->TCU) 104-bits (TCU->TBU) |
AXI streaming port for the local TBU to/from the TCU |
|
IOBank0_ecc_intr |
MPFE |
wire |
1-bit |
IOBank0 ECC error interrupt to GIC. |
|
IOBank1_ecc_intr |
MPFE-lite |
wire |
1-bit |
IOBank1 ECC error interrupt to GIC. |
|
IOBank_0 |
IOBank0_CSR |
MPFE |
AXI-lite |
32-bit |
Access to IOBank0 IOSSM CSRs |
IOBank0_P0 |
MPFE |
AXI4 |
256-bit |
SDRAM access through 32-bit controller |
|
IOBank0_P1 |
MPFE |
AXI4 |
256-bit |
SDRAM access through 16-bit controller |
|
IOBank0_ecc_intr |
IOBank0 |
wire |
1-bit |
IOBank0 ECC error interrupt |
|
IOBank_1 |
IOBank1_CSR |
MPFE |
AXI-lite |
32-bit |
Access to IOBank1 IOSSM CSRs |
IOBank1_P0 |
MPFE |
AXI4 |
256-bit |
SDRAM access through 32-bit controller |
|
IOBank1_P1 |
MPFE |
AXI4 |
256-bit |
SDRAM access through 16-bit controller |
|
IOBank1_ecc_intr |
IOBank1 |
wire |
1-bit |
IOBank1 ECC error interrupt |
|
MPFE-lite |
MPFE_lite_CSR |
MPFE |
AXI-lite |
32-bit |
MPFE to MPFE-lite port for access to IOBank1 IOSSM CSRs |
MPFE_lite_P0 |
MPFE |
AXI4 |
256-bit |
MPFE to MPFE-lite port for access to IOBank1 Port 0 (32-bit controller) |
|
MPFE_lite_P1 |
MPFE |
AXI4 |
256-bit |
MPFE to MPFE-lite port for access to IOBank1 Port 1 (16-bit controller) |
|
IOBank1_ecc_intr |
IOBank1 |
wire |
1-bit |
IOBank1 ECC error interrupt to MPFE |